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Hardware structure for realizing SVC macroblock-level algorithm

A technology of hardware structure and algorithm, applied in electrical components, digital video signal modification, image communication, etc., can solve problems such as low coding efficiency and insufficient utilization of hardware performance.

Inactive Publication Date: 2015-04-29
VIMICRO ELECTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the existing video codecs, SVC is mostly implemented by software algorithms, rarely by hardware, and the performance of hardware is not fully utilized, resulting in low coding efficiency.

Method used

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  • Hardware structure for realizing SVC macroblock-level algorithm
  • Hardware structure for realizing SVC macroblock-level algorithm
  • Hardware structure for realizing SVC macroblock-level algorithm

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Embodiment Construction

[0014] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0015] figure 1 It is a schematic diagram of a hardware structure for realizing the SVC macroblock-level algorithm in the embodiment of the present invention. Such as figure 1 As shown, the hardware structure includes: a memory, an arbitration (Arbitrate) module, a data reading (Read Data) module, a prediction (Prediction) module, and a sending data (Send Data) module.

[0016] Wherein, the memory stores the basic layer data, and the data reading module, the predicting module, and the data sending module need to access the memory at the same time or at different times to obtain corresponding data, or store the processed data in the memory. In an embodiment of the present invention, the memory may be implemented by SRAM (Static Random Access Memory).

[0017] Th...

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PUM

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Abstract

The embodiment of the invention provides a hardware structure for realizing an SVC macroblock-level algorithm, and aims at improving the encoding efficiency. The hardware structure comprises a memory, an arbitration module, a data reading module, a prediction module and a data sending module, wherein the data reading module, the prediction module and the data sending module realize access to the memory through the arbitration module; the memory saves base layer data, and the data reading module, the prediction module and the data sending module access the memory simultaneously or non-simultaneously; the arbitration module is used for judging the reading and writing priority of the data reading module, the prediction module and the data sending module to the memory; the prediction module is used for carrying out luminance sampling interpolation operation and chroma sampling interpolation operation on the data read from the memory by the data reading module to obtain luminance and chroma prediction values; SAD of the prediction values with the luminance information of the current frame is calculated, and finally the prediction values are saved in the memory.

Description

technical field [0001] The present invention relates to the SVAC standard, in particular to a hardware structure for realizing the SVC macroblock-level algorithm in the SVAC standard. technical background [0002] In existing video codecs, SVC is mostly realized through software algorithms, and rarely through hardware, and the performance of hardware is not fully utilized, resulting in low coding efficiency. Contents of the invention [0003] In view of this, an embodiment of the present invention provides a hardware structure for implementing an SVC macroblock-level algorithm, so as to improve coding efficiency. [0004] In order to achieve the above object, the embodiment of the present invention provides a hardware structure for realizing the SVC macroblock level algorithm, including: a memory, an arbitration module, a data reading module, a prediction module, and a data sending module; wherein the data reading module and the prediction module . The sending data module...

Claims

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Application Information

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IPC IPC(8): H04N19/42H04N19/433
Inventor 张鹏钟俊华
Owner VIMICRO ELECTRONICS CORP
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