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Semiconductor device and preparation method for suppressing creepage phenomenon

A technology for power semiconductors and devices, applied in the field of power semiconductor devices and their preparation, can solve problems such as the inability to suppress creepage phenomenon and the limited effect of creepage distance.

Active Publication Date: 2018-03-20
ALPHA & OMEGA SEMICON INT LP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The methods involved in the above literature have very limited effects on changing the creepage distance, especially when high voltage is applied to the drain or source pin, it is impossible to suppress the creepage phenomenon in harsh environments

Method used

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  • Semiconductor device and preparation method for suppressing creepage phenomenon
  • Semiconductor device and preparation method for suppressing creepage phenomenon
  • Semiconductor device and preparation method for suppressing creepage phenomenon

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Embodiment Construction

[0039] figure 2 A part of a lead frame 100 made of metal is shown, and now we still use the industry-standardized TO single-in-line package series as an example for follow-up explanation. The lead frame 100 usually includes a plurality of chip mounting units 110, such as Figure 3AEnlarged view shown. Each chip mounting unit 110 includes at least one generally square metal mounting base 111 or base island for carrying and adhering chips, and an edge 111a in a pair of opposite side edges of the base 111 Nearby, a plurality of parallel pins 113, 114, 155 or some larger number of unillustrated pins are provided, wherein the pins 113, 114 are disconnected from the base 110, while the pin 115 is connected to the base 110. 110 , pin 114 is arranged in the middle of pins 113 and 115 . In a pair of side edges of the base 111, a fork-shaped cooling fin 112 is connected to the other edge opposite to the edge 111a, and a slit is provided between the forks of the cooling fin 112, and i...

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Abstract

The invention relates to a semiconductor device, in particular to a power device with optimized creepage distance and a preparation method thereof. There is a chip mounting unit, the chip mounting unit includes a base and some pins, and the side-by-side pins are arranged in a non-equidistant manner and are located near one side edge of the base, a chip is adhered to the base, a plastic package The base and the chip are covered, and the plastic package includes a plastic package extension to cover at least a part of the pins to obtain a better electrical safety distance between the pins, so as to improve the voltage creepage distance of the device.

Description

technical field [0001] The present invention generally relates to a semiconductor device, and more specifically, the present invention aims to provide a power semiconductor device with optimized electrical clearance and increased voltage creepage distance (Creep-age distance) and a preparation method thereof for use in semiconductor devices A better electrical safety distance is obtained between the terminals. Background technique [0002] In traditional power semiconductor devices, large currents or high voltages usually flow between pins, and with the development of mainstream technologies, it is often necessary to sufficiently reduce the size of the device to meet the requirements of light weight, and the corresponding negative The effect is that the insulating material around the pins that are very close to each other is easily polarized, causing the insulating material to be electrified, affecting the normal operation of the device, and serious situations will bring saf...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/49H01L23/31H01L21/60H01L21/56
CPCH01L24/97H01L2224/0603H01L2224/32245H01L2224/48247H01L2224/49111H01L2224/73265H01L2924/13055H01L2924/13091H01L2224/97H01L2924/00
Inventor 牛志强哈姆扎·耶尔马兹鲁军王飞
Owner ALPHA & OMEGA SEMICON INT LP