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Semiconductor arrangement with electrostatic discharge (ESD) protection

An electrostatic discharge and semiconductor technology, which is applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve problems such as inoperability and poor operability of equipment

Active Publication Date: 2015-08-05
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Electrostatic discharge events have been known to render equipment less operable than expected or inoperable at all

Method used

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  • Semiconductor arrangement with electrostatic discharge (ESD) protection
  • Semiconductor arrangement with electrostatic discharge (ESD) protection
  • Semiconductor arrangement with electrostatic discharge (ESD) protection

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Embodiment Construction

[0030] The claimed subject matter will now be described with reference to the drawings, wherein like reference numerals generally refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide an understanding of claimed subject matter. It may be evident, however, that claimed subject matter may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

[0031] The present invention provides one or more semiconductor arrangements comprising one or more semiconductor devices. In some embodiments, the semiconductor arrangement includes an electrostatic discharge (ESD) device. In some embodiments, the semiconductor arrangement forms at least one of a three-dimensional integrated circuit (3D IC), a 2.5-dimensional integrated circuit (2.5D IC), and a monolithic integra...

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Abstract

One or more semiconductor arrangements having a stacked configuration and electrostatic discharge (ESD) protection are provided. The semiconductor arrangements include a first substrate, a second substrate, an ESD pad, an ESD device and a first interlayer via connecting the first substrate and the second substrate. The first substrate includes a first PMOS device and a first device and the second substrate includes a first NMOS device and a second device. Alternatively, the first substrate includes a first PMOS device and a first NMOS device and the second substrate includes a first device and a second device.

Description

technical field [0001] The present invention relates generally to integrated circuits, and more particularly to three-dimensional integrated circuits (3D ICs). Background technique [0002] In electronics, a three-dimensional integrated circuit (3D IC) is a device that integrates two or more layers of active electronic components into a single circuit. Like other circuits, 3D integrated circuits are susceptible to electrostatic discharge (ESD) events. An electrostatic discharge event is a sudden and unpredictable voltage or current that transfers energy to a device. Electrostatic discharge events have been known to render equipment less operable than expected or inoperable at all. Contents of the invention [0003] According to an aspect of the present invention, there is provided a semiconductor arrangement including: a first substrate, a second substrate, an electrostatic discharge (ESD) pad, and a first interlayer via. The first substrate includes: a first PMOS devic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L2225/06541H01L25/0657H01L27/092H01L27/0629H01L23/60H01L23/5226H01L27/0251H01L2924/0002H01L27/0688H01L23/481H01L25/16H01L25/18H01L2924/00H01L27/0248H01L27/04Y10S257/906
Inventor 陈佳惠马威宇陈国基
Owner TAIWAN SEMICON MFG CO LTD