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Delay Line Circuit With Variable Delay Line Unit

A delay cell, delay line technology used in electrical components, single output arrangements, static memory, etc. to solve problems such as inconsistent step changes, increased clock jitter, etc.

Active Publication Date: 2015-08-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Inconsistent step changes or delays increase clock jitter

Method used

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  • Delay Line Circuit With Variable Delay Line Unit
  • Delay Line Circuit With Variable Delay Line Unit
  • Delay Line Circuit With Variable Delay Line Unit

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0029] The following disclosure presents a number of different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first part on or over a second part may include an embodiment in which the first part and the second part are formed in direct contact, and may also include an embodiment in which the first part and the second part Additional components may be formed in between such that the first and second components are not in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purposes of simplicity and clarity, and by itself does not indicate a relationship between the various embodiments and / or structures...

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Abstract

A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line.

Description

technical field [0001] The present invention relates to delay line circuits with variable delay line elements. Background technique [0002] Device manufacturers are challenged, for example, to develop integrated circuits with high-quality performance in order to bring value and convenience to customers. Double data rate circuits use delay lines and delay data or clock delays to achieve proper signal timing during data transmission. The delay line provides linear steps, which are used to tune the received input signal. Inconsistent step changes or delays increase clock jitter. Contents of the invention [0003] In order to solve the problems existing in the prior art, according to one aspect of the present invention, a delay line circuit is provided, including: a plurality of delay units configured to receive an input signal and change the input signal to generate a first output signal, the plurality of delay cells configured to selectively invert or relay the input sig...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/14
CPCH03K2005/00019H03K5/14H03K5/133H03K2005/00071G11C5/063G11C7/1066G11C7/222G11C11/4076
Inventor 黃明杰陈建宏黄琮靖林志昌薛福隆
Owner TAIWAN SEMICON MFG CO LTD