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A circuit that uses negative voltage to enter chip test mode

A chip testing, negative voltage technology, applied in the direction of logic circuits, electrical components, pulse technology, etc., can solve the problems of increasing chip cost and design complexity

Inactive Publication Date: 2017-12-22
XINBAI MICROELECTRONICS BEIJING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The above method involves non-volatile storage modules such as OTP, MTP and flash, which will increase the chip cost and design complexity

Method used

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  • A circuit that uses negative voltage to enter chip test mode

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Embodiment Construction

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0014] see figure 1 , a circuit that uses a negative voltage to enter a chip test mode, including a switch M0, a switch M1, a resistor R0 and a NOT gate circuit I9, the source of the switch M0 is connected to the power supply VDD, and the drain of the switch M0 is connected to the tube The pin P1 and the drain of the switch tube M1, the gate of the switch tube M0 are connected to the resistor R0, the gate of the switch tube M1, the gate of the switch tube M2 a...

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Abstract

The invention discloses a circuit for entering a chip test mode by using a negative voltage, comprising a switch tube M0, a switch tube M1, a resistor R0 and a NOT gate circuit I9, the source of the switch tube M0 is connected to a power supply VDD, and the drain of the switch tube M0 The pole is connected to the pin P1 and the drain of the switch M1, the gate of the switch M0 is connected to the resistor R0, the gate of the switch M1, the gate of the switch M2 and the gate of the switch M3. The present invention proposes a circuit that multiplexes I / O pins and needs to cooperate with the application of negative voltage to enter the test mode. Under the condition that the process does not have non-volatile storage, it can still have multiple state modes after chip packaging , and will not affect the normal application of customers.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and proposes a circuit that reuses I / O pins and needs to cooperate with the application of negative voltage to enter a test mode, simplifies the production test process, and facilitates analysis and debugging when a problem occurs in the chip. Background technique [0002] Various failures may occur in the semiconductor process: material defects and process deviations may cause problems such as short circuits, open circuits, and device-junction punch-through in the chip. Such physical failures will inevitably lead to failures in circuit function or performance. [0003] Through effective testing methods, it is used to locate faults in the manufacturing process and ensure the correctness of basic components such as wiring and transistors. The original design needs to be modified to include test logic that is only used during testing. Test logic not only facilitates the automatic generati...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/00
Inventor 阮为
Owner XINBAI MICROELECTRONICS BEIJING
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