Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory

A non-volatile, memory technology, applied in the direction of memory system, data processing power supply, protection of stored content to prevent loss, etc., can solve incomplete or easy, laborious and other problems

Active Publication Date: 2016-08-31
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This is a laborious process for customers using this computing or processing device, which can lead such customers to hire application engineers to

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  • Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory
  • Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory
  • Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory

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Embodiment Construction

[0013] Now turning to the graph, especially figure 1 , an example computing device device compatible with many of these teachings will now be described. Computing device 100 includes a central processing unit (“CPU”) 105 , a memory subsystem 110 , nonvolatile memory 115 , and a number of peripherals or device modules 120 . The power management unit 130 or peripheral power sensing device 135 is configured to detect the presence or absence of power for the CPU 105 . Each of these elements is individually known in the art such that no further description is required. For example, non-volatile memory 115 is part of non-volatile subsystem 140 , which includes non-volatile controller 145 . The NVL memory 115 itself may be a flash-type memory, a state retention technology based on Ferromagnetic Random Access Memory ("FRAM") (which combines the characteristics of FRAM memory with current data retention methods), or a magneto-resistive Other technologies of similar character as Ran...

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Abstract

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

Description

[0001] Related applications [0002] This application claims the benefit of US Provisional Application No. 62 / 120,830, filed February 25, 2015, which is incorporated herein by reference in its entirety. technical field [0003] This disclosure relates generally to processing devices with non-volatile memory, and in particular to operations for entering and exiting deep low power modes for such processing devices. Background technique [0004] Electronic devices are constantly facing performance pressures including providing increased computing power and providing varying control capabilities. The performance pressures also include the ever-increasing capacity required to extend battery life or generally improve the power efficiency of operation of computing devices. Accordingly, various types of computing devices incorporate different ways of entering low power modes that allow a given device to use less power. Low power modes typically include disabling various features ...

Claims

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Application Information

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IPC IPC(8): G06F12/16G06F1/32
CPCG06F1/3212G06F1/3225G06F12/16G06F1/3243G06F1/3275G06F1/3287G06F9/4418Y02D10/00Y02D30/50G06F12/0246G06F2212/7203
Inventor A·丹嫩贝格B·彼得森A·K·吴J·施赖纳M·茨韦格S·C·巴特林
Owner TEXAS INSTR INC
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