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A memory compiler splicing method and memory

A memory and compiler technology, applied in the field of memory, can solve problems such as memory area waste, and achieve the effect of reducing area waste and enhancing area utilization.

Active Publication Date: 2019-01-04
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In view of this, the present application provides a memory compiler splicing method for solving the problem of memory area waste in the prior art

Method used

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  • A memory compiler splicing method and memory
  • A memory compiler splicing method and memory
  • A memory compiler splicing method and memory

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Embodiment Construction

[0037] Aiming at the problem in the prior art that the size of the circuit in the memory functional module is determined according to the worst case of the array, thereby causing waste of memory area, the present application discloses a memory compiler splicing method and memory.

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0039] In the Fin Field-Effect Transistor (FinFET) process, the channel length of the MOS device is fixed, and the channel width can only be quantified. Therefore, the user can cust...

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Abstract

The present application discloses a splicing method of a memory compiler, which includes: determining the difference between the delay time of the signal driven from the word line to the farthest storage unit and the number n of columns of the storage unit and the number nWLD of Fins driving the MOS driven by the word line The functional relationship between; the storage units in n columns are divided into i sections, and the delay tn / i of storage units in n / i columns is calculated within the value range of nWLD; when the delay tn / i is less than the first preset When setting the value, obtain the nWLD corresponding to the above-mentioned delay tn / i, which is recorded as nmeet; insert a buffer between every two memory cells, and drive the word line and drive each buffer as nmeet fins; assemble the layout, It can be seen that the word line driver of the memory cell and the number of Fins of the buffer obtained by the above method are both optimal values, thereby enhancing the area utilization rate of the memory and reducing area waste.

Description

technical field [0001] The present application relates to the technical field of memory, and more specifically, to a memory compiler splicing method and memory. Background technique [0002] In the design process of the existing memory compiler, the memory is usually divided into various functional modules (leaf cells), and the circuit size of the functional modules is determined according to the worst case of the array. Then use the program to splice each functional module according to the configuration parameters, and finally combine multiple functional modules into a memory. In this process, the large-scale devices in the memory are all set according to the worst case of the array, and the changes in the number of rows and columns of the array cannot be tracked. Therefore, the memory generated by the technical solution in the prior art Area (Performance, power, area—referred to as PPA) is wasted, and memory power consumption will also be increased. Contents of the inve...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 杨杨
Owner SPREADTRUM COMM (SHANGHAI) CO LTD