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Secure block of ram with multiple partitions

A technology of area and memory block, which is applied in the direction of instruments, preventing unauthorized use of memory, electrical digital data processing, etc.

Active Publication Date: 2019-07-05
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the key is stored in memory for use during decryption, it is desirable to protect and restrict access to the key

Method used

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  • Secure block of ram with multiple partitions
  • Secure block of ram with multiple partitions
  • Secure block of ram with multiple partitions

Examples

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Embodiment Construction

[0041] figure 1 It is a simplified partial block diagram of an exemplary high-density programmable logic device 100 in which techniques according to the present invention can be used. The PLD 100 includes a two-dimensional array of programmable logic array blocks (LAB) 102 interconnected by a network interconnected by rows and columns of variable length and speed. The LAB 102 includes multiple (for example, 10) logic elements (LEs), which are small logic units that provide efficient implementation of user-defined logic functions.

[0042] The PLD 100 also includes a distributed memory structure that includes RAM blocks of variable size provided throughout the array. The RAM block includes, for example, a 512-bit block 104, a 4K block 106, and an M block 108 that provides 512K-bit RAM. These memory blocks can also include shift registers and FIFO buffers. The PLD 100 also includes, for example, a digital signal processing (DPS) block 110 that can implement a multiplier with add...

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PUM

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Abstract

Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.

Description

[0001] Cross references to related applications [0002] This application is a partial continuation of U.S. Patent Application No. 12 / 830,447 filed on June 6, 2010. U.S. Patent Application No. 12 / 830,447 was filed on September 7, 2006 and titled "SECURITY RAM BLOCK" A divisional application of US Patent Application No. 11 / 517,689 (now US Patent No. 7,752,407), the entire contents of all these applications are incorporated into this application by reference. Background technique [0003] The present invention relates generally to storing data on integrated circuits, and more specifically to protecting data stored in battery-powered memory on a field programmable gate array (FPGA). [0004] The circuit complexity and tasks performed by integrated circuits such as field programmable gate arrays have increased tremendously in the past few years. Highly complex software or applications that are configured to perform complex user-defined functions run on programmable logic elements. [000...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/14G06F21/76G06F21/79G06F21/81
CPCG06F21/76G06F2221/2141G06F2221/2143
Inventor M·朗哈默
Owner INTEL CORP