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Embedded logic analyzer and integrated circuit including the embedded logic analyzer

A logic analyzer, integrated circuit technology, applied in logic circuits, multiple input and output pulse circuits, instruments, etc., can solve the problems of increasing chip size and reducing productivity

Active Publication Date: 2020-06-26
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Chip size increases and productivity decreases because many input-output pins are allocated for extracting internal signals

Method used

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  • Embedded logic analyzer and integrated circuit including the embedded logic analyzer
  • Embedded logic analyzer and integrated circuit including the embedded logic analyzer
  • Embedded logic analyzer and integrated circuit including the embedded logic analyzer

Examples

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Embodiment Construction

[0057] Detailed example embodiments of the inventive concepts are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the inventive concepts. Example embodiments of the inventive concepts may, however, be embodied in many alternative forms and should not be construed as limited to only the embodiments set forth herein.

[0058] Therefore, although example embodiments of the inventive concepts are capable of various modifications and alternative forms, the embodiments of the inventive concepts will be shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intention to limit example embodiments of the inventive concepts to the particular form disclosed, but on the contrary, example embodiments of the inventive concepts cover all modifications, Equivalents and Alternatives. Like numbers refer t...

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Abstract

Provided are an embedded logic analyzer and an integrated circuit including the embedded logic analyzer. An embedded logic analyzer for an integrated circuit comprising: a compare block configured to: generate a capture data signal and a plurality of compare enable signals based on an input data signal from one of the functional blocks included in the integrated circuit such that The plurality of enable signals are respectively activated based on different comparison conditions; the operation block is configured to: perform a logic operation on the plurality of comparison enable signals to generate a data enable signal indicating a data capture timing; a packager circuit system , configured to: generate a packetizer data signal including capture data and capture time information based on the capture data signal, the data enable signal, and the time information signal.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2015-0114422 filed with the Korean Intellectual Property Office (KIPO) on Aug. 13, 2015, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Example embodiments relate generally to semiconductor integrated circuits, and more particularly, to an embedded logic analyzer and an integrated circuit including the embedded logic analyzer. Background technique [0003] When the developed integrated circuit operates abnormally, a debugging process is performed to search and solve the problem. Functional blocks (such as central processing units (CPUs), digital signal processors (DSPs), etc.) connected to the main bus may be debugged using a Joint Test Action Group (JTAG) framework or the like. In order to debug circuits that are not directly connected to the main bus, such as the internal logic of a modem block, the internal signals must be extracted to an e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3177
CPCG01R31/3177G01R31/31705H03K19/1737H03K19/17764H03K5/26
Inventor 高浚源
Owner SAMSUNG ELECTRONICS CO LTD