Branch prediction control method and branch prediction control device

Abstract

The invention discloses a branch prediction control method and a branch prediction control device. The branch prediction control method includes subjecting a branch instruction to branch prediction during instruction fetching, and subjecting a branch target to instruction fetching; subjecting the branch instruction to branch prediction again during decoding; when a branch prediction result obtained during decoding needs to be used for correcting a branch prediction result obtained during instruction fetching, recording a current instruction fetching PC to an instruction re-fetching PC register, and subjecting the branch target for branch prediction during decoding to instruction fetching; when the branch instruction completes branch judgment, judging whether correction is correct or not according to a branch judgment result; if yes, continuing the branch target for branch prediction during decoding and subsequent instruction fetching operation, and flushing subsequent instructions of the branch instruction; if not, cancelling the branch target for branch prediction during decoding, and performing instruction fetching according to a PC in the instruction re-fetching PC register. The branch prediction control method is capable of reducing misprediction penalties of the branch prediction during decoding and improving branch instruction execution efficiency.

Description

technical field [0001] The present invention relates to the technical field of processors, in particular to a branch prediction control method and device. Background technique [0002] There are a large number of branch instructions in the program, and branch instructions are also called transfer instructions and jump instructions. Under normal circumstances, the processor fetches instructions in order of instruction addresses. For example, the current instruction fetch PC is the instruction fetch PC+4 of the previous cycle (assuming that each instruction fetch fetches 4 bytes). However, before the branch instruction is executed, the processor cannot determine the address of the next instruction, and even before the instruction is decoded, it cannot determine whether the instruction is a branch instruction. If the instruction fetching unit fetches instructions in an unconditional order, after the branch instruction executes the branch, all subsequent instructions fetched ne...

AI Technical Summary

Problems solved by technology

With this method, the misprediction loss of branch prediction is large during decoding, which reduces the execution efficiency of branch instructions.

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