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A server failure recovery system and method using redundant PCH
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A fault recovery and server technology, applied to hardware redundancy for data error detection, instrument, response error generation, etc., can solve problems such as system failure and achieve reliable design principles, wide application prospects, and significant progress Effect
Active Publication Date: 2020-09-29
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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[0004] The object of the present invention is to provide a server failure recovery system and method using redundant PCH to solve the above technical problems
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Embodiment 1
[0046] Example 1 as figure 1 As shown, the present invention provides a server fault recovery system that adopts redundant PCH, including management controller BMC 1, BIOS chip 2, south bridge chip PCH, the first CPU board 5, the second CPU board 6, the third CPU board 7. The fourth CPU board 8, the first CPU board 5 has the first CPU 9 and the second CPU 10, the second CPU board 6 has the third CPU 11 and the fourth CPU 12, and the third CPU board 7 has the fifth CPU 13 and the sixth CPU 14, the seventh CPU 15 and the eighth CPU 16 are arranged on the fourth CPU board 8, the first CPU 9 is the master CPU, and the rest are slave CPUs;
[0047] The south bridge chip PCH includes a first south bridge chip PCH 3 and a second south bridge chip PCH 4, the first south bridge chip PCH 3 is a working south bridge chip PCH, and the second south bridge chip PCH 4 is a redundant south bridge chip PCH; The first south bridge chip PCH 3 and the second south bridge chip PCH 4 are on an ind...
Embodiment 2
[0051] Example 2 as figure 2 As shown, a method for recovering from a server failure using redundant PCHs includes the following steps:
[0052]Step 1. Set the main CPU, and set the south bridge chip PCH connected to the main CPU as the working south bridge chip PCH by default;
[0053] Step 2. The server tries to boot;
[0054] Step 3. The working south bridge chip PCH obtains the setting information of the system stored in the BIOS chip, the device driver and the self-test program and transmits them to the main CPU;
[0055] Step 4. If the main CPU does not fail, the main CPU loads the self-test program and performs self-test. If there is no failure from the CPU, go to step 7. If there is a failure from the CPU, go to step 6;
[0056] If the main CPU fails and the self-test program cannot be loaded, go to step 5;
[0057] Step 5. The work south bridge chip PCH reports to the management controller BMC;
[0058] The management controller BMC configures the faulty master C...
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Abstract
The invention provides a server fault recovery system and method using a redundant PCH (Platform Controller Hub). The server fault recovery system using the redundant PCH comprises a management controller BMC, a BIOS chip, a platform controller hub PCH and a plurality of CPU boards; each CPU board comprises a plurality of CPUs; only one of the CPUs included in all CPU boards is a main CPU, and the rest CPUs are slave CPUs; the platform controller hub PCH comprises a working platform controller hub PCH and the redundant platform controller hub PCH; the number of the redundant platform controller hub PCH is at least one and is the number of the slave CPUs at most; the working platform controller hub PCH is connected with the main CPU through a DIM bus; the redundant platform controller hub PCH is connected with the slave CPUs through DMI buses; the platform controller hub PCH is connected with the BIOS chip; the management controller BMC is connected with the CPU boards; the management controller BMC is connected with the platform controller hub PCH; the CPUs are connected with each other through buses.
Description
technical field [0001] The invention belongs to the field of server failure recovery, and in particular relates to a server failure recovery system and method using redundant PCHs. Background technique [0002] In an eight-way server design, a south bridge chip (PCH, platform controller hub) is usually used to connect to a CPU through the DMI bus. This CPU is called the main CPU and is responsible for data interaction with the PCH. When the system is turned on, PCH obtains system setting information, device drivers, and self-inspection programs from the BIOS, and completes the self-inspection of all CPUs and memory through the DMI bus with the main CPU. After the self-test is completed, the BIOS will start to guide the operating system and complete the boot. In this design, the system can shield the faulty slave CPU, but if the master CPU fails, the DMI bus between the PCH and the PCH cannot work, the BIOS program cannot be loaded, the system cannot shield the master CPU, a...
Claims
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