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Integrated circuit and method for detecting malicious code in a first-level instruction cache

A high-speed cache, integrated circuit technology, applied in the field of malicious code

Active Publication Date: 2018-09-25
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the ability to execute code without accessing the L2 cache may allow an adversary to replace harmless code that uses the L2 cache with malicious / corrupt code that does not use the L2 cache without the replacement being detected

Method used

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  • Integrated circuit and method for detecting malicious code in a first-level instruction cache
  • Integrated circuit and method for detecting malicious code in a first-level instruction cache
  • Integrated circuit and method for detecting malicious code in a first-level instruction cache

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Embodiment Construction

[0016] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" need not be construed as being preferred or advantageous over other embodiments.

[0017] See figure 2 with 3 One aspect of the present invention may lie in the integrated circuit 210, which includes a processor 220, a first-level instruction cache 230 with a first storage capacity, and a second-level high-speed cache with a second storage capacity greater than the first storage capacity. Buffer memory 240. The first-level instruction cache is coupled between the processor and the second-level cache, and is configured to store a subset of the instructions stored in the second-level cache. The second-level cache is coupled between the first-level instruction cache and the external memory 250, and is configured to store a subset of the data and instructions stored in the external memory. The processor is configured to execute the i...

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PUM

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Abstract

The present invention provides an integrated circuit, which may include: a processor; a first-level instruction cache having a first storage capacity; and a second-level cache having a second higher than the first storage capacity. storage. The first level instruction cache is configured to store a subset of the instructions stored in the second level cache. The second level cache memory is configured to store a subset of the data and instructions stored in the external memory. The processor executes an inner loop of a detection routine and monitors the execution time of the inner loop to detect malicious code in the first level instruction cache. The total number of detection routine instructions is greater than the first storage capacity. The inner loop requires detection routine instructions to be fetched from the second level cache, and an execution number of instructions executed during execution of the inner loop is less than the first storage capacity.

Description

[0001] Cross reference to related applications [0002] This application claims the priority and rights of U.S. non-provisional application No. 14 / 493,306 filed with the U.S. Patent Office on September 22, 2014, and the entire content of the application is incorporated herein by reference. Technical field [0003] The present invention generally relates to detecting malicious code associated with do-not-cache attacks. Background technique [0004] Many computing environments contain instructions that fetch one or more instructions directly from RAM. These instructions are not stored in the second level (L2) cache memory, but instead are directly copied to the smaller and faster first level (L1) instruction cache memory. Generally, bypassing the L2 cache is a benign operation. However, the ability to execute code without accessing the L2 cache may allow the enemy to replace the harmless code using the L2 cache with malicious / corrupted code that does not use the L2 cache without the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0811G06F12/0875G06F12/0897G06F12/14
CPCG06F12/0811G06F12/0875G06F12/0897G06F12/14G06F21/563G06F2212/1052G06F2221/033
Inventor B·M·雅各布松
Owner QUALCOMM INC