Digital logic circuit with stable reset control

Abstract

The invention discloses a digital logic circuit with stable reset control. The digital logic circuit comprises an input end rst_in, a stable reset control module and an output end rst_out, wherein thestable reset control module is provided with a clock signal clk_in input end and a reset control signal PAD_RESETN input end, the reset control signal PAD_RESETN input end is used for receiving a reset control signal PAD_RESETN sent by the output end rst_out, and the stable reset control module also comprises a deburring stable unit, a state machine unit and a stable signal generation unit. Besides, the digital logic circuit supports a DFT, a test mode control signal test_mode enables the output end rst_out to be equal to the input end rst_in of the digital logic circuit, and therefore it isensured that reset R of the digital logic circuit is completely controllable.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to the logic design of chip hardware, in particular to a digital logic circuit with stable reset control. Background technique [0002] Digital logic circuits are divided into two categories according to their structural characteristics: combinational logic circuits (referred to as combinational circuits) and sequential logic circuits (referred to as sequential circuits). The sequential logic circuit is a logic circuit with a memory function, and the memory element generally adopts a D type flip-flop (DFF for short). [0003] D flip-flops are widely used and can be used as digital signal registers, shift registers, frequency division, and waveform generators. D flip-flop is an information storage device with memory function and two stable states (0 or 1). It is the most basic logic unit that constitutes a variety of sequential circuits, and it is also an important unit ...

AI Technical Summary

Problems solved by technology

[0010] However, the current reset deglitch circuit in the industry is implemented by using a conventional D flip-flop with a reset circuit, but during the asynchronous reset operation of the chip, the clock / reset functions in the conventional D flip-flop with a reset circuit may be mutually dead. In addition, some sequential logic circuit units require only 1ms for input and reset, but the relevant supporting modules take longer (such as 50ms) to complete the initialization, and the simple deburring circuit cannot meet the demand

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