Memory member and operation method

Abstract

A memory member includes an unit array, a control circuit and a controller of an adjacent area. The unit array comprises a main region and an adjacent region. A plurality of main memory units are arranged in the main region and the plurality of adjacent memory units are arranged in the adjacent region. The control circuit is used for controlling column operation and list operation. The controllerof the adjacent region is used for controlling an adjacent memory unit to make the adjacent memory unit operate under a condition different from that of the main memory unit.

Description

[0001] Cross References to Related Applications [0002] This patent application claims priority from Korean Patent Application No. 10-2016-0088089 filed on July 12, 2016 at the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] Embodiments of the present invention relate to a memory device and a method of operating the same. Background technique [0004] A memory cell of a semiconductor memory device such as a dynamic random access memory (DRAM) includes a transistor serving as a switch and a capacitor storing charge (data). Data stored in a memory cell may be logic high (1) or logic low (0) depending on whether charge is stored in the memory cell (ie, whether the terminal voltage of the capacitor is high or low). [0005] Storing data requires maintaining a charge in a capacitor. However, the initial charge stored in the capacitor may deteriorate over time due to leakage curren...

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Problems solved by technology

[0007] Also, when the data retention time of some memory cells included in the memory device does not exceed a defined reference time during the test process of the memory device, the memory device is handled as failed, and the memory device is discarded

Of course this leads to lower yields in the manufacturing process of memory devices

[0008] Furthermore, even memory devices that have passed initial quality testing can introduce errors when weak cells are present due to post-manufacturing reasons

[0009] As the number of cells integrated in a single chip has increased to tens of millions or more, the probability that a weak cell will appear has also increased despite improvements in manufacturing processes

Unless precise testing is performed on such weak cells, the reliability of semiconductor memory devices cannot be ensured

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