A layout boundary extraction method and device
A boundary extraction and layout technology, applied in image analysis, image data processing, instruments, etc., can solve problems such as difficulties in designing memory
Active Publication Date: 2020-09-29
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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[0002] With the continuous improvement of semiconductor manufacturing technology and integrated circuit design capabilities, the number of memories used in SoC (System-on-Chip, system-on-chip) is increasing, because various memories of different sizes or structures are required in the same design , it becomes very difficult to design these memories with a full custom approach
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[0063] In order to enable those skilled in the art to better understand the embodiments of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0064] see figure 1 , which shows a flowchart of a layout boundary extraction method provided by an embodiment of the present invention, which may include the following steps:
[0065] 101: Obtain the vertices of each rectangular sub-module in the layout of the integrated circuit.
[0066] In the embodiment of the present inv...
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The invention provides a layout boundary extraction method and device. Vertices of all rectangular sub-modules in an integrated circuit layout are acquired; boundary extraction is carried out on the rectangular sub-modules in the integrated circuit layout; a module is combined with other uncombined rectangular sub-modules and / or other modules, boundary extraction is carried out on a module, whichis obtained after each time of combination, until a module after combination is the integrated circuit layout; and vertices of constituent main-bodies combined into the integrated circuit layout are used as a basis to integrate boundaries of the constituent main-bodies to obtain boundaries of the integrated circuit layout. Using the vertices of the rectangular sub-modules and / or the modules as thebasis to acquire the boundaries of the integrated circuit layout is realized, the vertices of the multiple sub-modules and / or modules can be simultaneously acquired when the vertices of the rectangular sub-modules and / or the modules are used as the basis to acquire the boundaries, and boundary extraction for the multiple sub-modules and / or modules is realized.
Description
technical field [0001] The invention relates to the technical field of integrated circuit layout, in particular to a layout boundary extraction method and device. Background technique [0002] With the continuous improvement of semiconductor manufacturing technology and integrated circuit design capabilities, the number of memories used in SoC (System-on-Chip, system-on-chip) is increasing, because various memories of different sizes or structures are required in the same design , it becomes very difficult to design these memories completely with a full-custom approach. Memory compilers are widely used as efficient tools for generating memories of different sizes and functions. [0003] In the use of the memory compiler, it is first necessary to quickly obtain the boundary of the generated memory IP (Intellectual Property, silicon intellectual property) core; and in order to protect the core technology of the memory compiler developer, provide the interface information of t...
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IPC IPC(8): G06T7/13G06F30/392
Inventor 陈岚陈巍巍龙爽王家蕊
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI