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Packaging device

A technology of sealing and dielectric layer, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., and can solve the problems of the number of electrical contacts and the adverse effects of electrical properties against flexibility

Active Publication Date: 2018-02-23
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Accordingly, various characteristics of the packaged die / package (e.g., number of electrical contacts, electrical performance, stiffness, etc.) may be adversely affected

Method used

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Embodiment Construction

[0075] The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the invention. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the description below that a first feature is formed "on" a second feature or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first feature is formed in direct contact. Embodiments where an additional feature may be formed between a feature and a second feature such that the first feature may not be in direct contact with the second feature. Additionally, this disclosure may repeat reference numbers and / or letters in various instances. This repetition is for the purposes of brevity and clarity and does not in itself indicate a re...

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PUM

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Abstract

One embodiment of the present invention provides a packaging device. The packaging device includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The second dielectric layer is formed on the first dielectric layer, and includes a device substrate and a through hole extending from the first dielectric layer and penetrating through the second dielectric layer. Thethird dielectric layer is formed on the second dielectric layer, and includes a conductive pillar extending from and penetrating the third dielectric layer, wherein the conductive pillar is electrically coupled to the through hole of the second dielectric layer.

Description

technical field [0001] Embodiments of the invention relate to a packaged device. Background technique [0002] Since the invention of the integrated circuit, the semiconductor industry has experienced continuous rapid development due to the increasing integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In large part, these increases in integration density have come from successive reductions in minimum feature size, which has enabled more components to be integrated into a given chip area. [0003] These improvements in integration are essentially two-dimensional (2D) in nature, since the volume occupied by the integrated components is located essentially on the surface of the semiconductor wafer. Although significant improvements in lithography have allowed for considerable improvements in the formation of two-dimensional integrated circuits, there are, however, physical limits to the densities that can be achieved i...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L21/48
CPCH01L23/49822H01L23/49827H01L21/4857H01L21/486H01L2224/73267H01L2924/15311H01L2924/181H01L2224/12105H01L2224/16225H01L2224/18H01L2224/32225H01L23/5389H01L23/49816H01L21/568H01L21/6835H01L2221/68359H01L2221/68372H01L2221/68345H01L24/19H01L24/16H01L24/32H01L24/73H01L24/24H01L24/82H01L2224/82001H01L24/29H01L2924/00012H01L21/76802H01L21/76877H01L21/76885H01L21/76895H01L23/3128H01L23/5384H01L23/5386H01L24/20H01L24/81H01L2224/02379H01L2224/0239H01L2224/024H01L2224/04105H01L2224/13014H01L2224/13016H01L2224/13024H01L2224/16227H01L2224/211H01L2224/214H01L2224/215H01L2224/29111H01L2224/29139H01L2224/29147H01L2224/29155H01L2224/29166H01L2224/2919H01L2224/32245H01L2224/92244H01L2924/01029H01L2924/06H01L2924/0665H01L2924/07025
Inventor 普翰屏李孝文
Owner TAIWAN SEMICON MFG CO LTD