Display system and display method

Abstract

The invention discloses a display system and a display method. The display system comprises a display, a SOC chip, an FPGA chip and a controller, wherein the SOC chip is connected to an external hostand outputs a first signal sent by the external host; the FPGA chip is coupled to the display and the SOC chip; the FPGA chip includes an interface module and an image processing module; the interfacemodule is used for receiving the first signal output by the SOC chip; the image processing module is used for receiving the first signal and processing data corresponding to the first signal so as tooutput a second signal; and the controller is coupled to the FPGA chip and is used for sending the second signal output by the image processing module to the display when connection between the SOC chip and the interface module is stable. In the invention, when the connection between the SOC chip and the interface module of the FPGA chip is stable, under the control of the controller, the FPGA chip outputs a video signal to the display so that problems of display frame flicker of the display caused by unstable connection between the SOC chip and the interface module and long boot time causedby video signal delay output are avoided.

Description

technical field [0001] The invention belongs to the field of display technology, and in particular relates to a display system and a display method thereof. Background technique [0002] The existing medical display platform adopts the design method of SoC chip + FPGA chip. Architecture details see figure 1 . Many functions that cannot be realized by the Soc chip are transplanted to the FPGA chip, and the program of the Soc has been reduced accordingly, but according to the traditional process, the boot time is still long. After booting and powering on, the Soc loads the program and initializes the DDR, PLL, and UART ports. At the same time, the FPGA loads the configuration file. After the loading is completed, the MCU configures the parameters of the modules in the FPGA. For details, see figure 2 . [0003] During the entire boot process, how to ensure the stable data connection between Soc and FPGA chips is the key to the entire boot process. At the initial stage of ...

AI Technical Summary

Problems solved by technology

Although this measure improves the stability of the boot system to a certain extent, there is a problem that the boot time of Soc and FPGA is too long

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