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Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT)

A computer processor and memory instruction technology, applied in the field of memory instructions, can solve problems such as reducing processor performance

Inactive Publication Date: 2018-04-17
QUALCOMM INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Re-fetch and re-execution of memory instructions can reduce processor performance and generate greater power consumption

Method used

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  • Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT)
  • Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT)
  • Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT)

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Embodiment Construction

[0018] Referring now to the drawings, several exemplary aspects of the invention are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0019] Aspects disclosed in the detailed description include predicting memory instruction detachments in a computer processor using a detachment avoidance table (PAT). In this regard, figure 1 is a block diagram of an exemplary out-of-order (OOO) computer processor 100 that provides out-of-order processing of instructions to increase instruction processing parallelism. As discussed in more detail below, the OOO computer processor 100 includes instruction processing circuitry 102 that accesses a PAT 104 for speculative memory instruction detachment. As a non-limiting example, the term "memory instruction" as used herein generally refers to memory load instru...

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Abstract

Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT) are disclosed. In one aspect, an instruction processing circuit accesses a PAT containing entries each comprising an address of a memory instruction. Upon detecting a memory instruction in an instruction stream, the instruction processing circuit determines whether the PAT contains an entry having an address of the memory instruction. If so, the instruction processing circuit prevents the detected memory instruction from taking effect before at least one pending memory instruction older than the detected memory instruction, to preempt a memory instruction punt. In some aspects, the instruction processing circuit may determine, upon execution of a pending memory instruction, whether a hazard associated with the detected memory instruction has occurred. If so, an entry for the detected memory instruction is generated in the PAT.

Description

[0001] priority claim [0002] This application asserts the title "PREDICTING MEMORY INSTRUCTION PUNTS IN A COMPUTER PROCESSOR USING A PUNT AVOIDANCE TABLE (PAT)" filed on August 14, 2015. Priority to U.S. Provisional Patent Application No. 62 / 205,400," the contents of which are hereby incorporated by reference in their entirety. [0003] This application also asserts the application filed on September 24, 2015 entitled PREDICTING MEMORY INSTRUCTION PUNTS IN A COMPUTER PROCESSOR USING A PUNT AVOIDANCE TABLE (PAT) )”, the contents of which are incorporated herein by reference in their entirety. technical field [0004] The techniques of this disclosure relate generally to processing memory instructions in an out-of-order (OOO) computer processor, and specifically, to avoiding re-fetching and re-executing instructions due to conflicts. Background technique [0005] An out-of-order (OOO) processor is a computer processor capable of executing computer program instructions in ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3834G06F9/3838G06F9/3004G06F9/3842G06F9/3869
Inventor L·颜M·W·莫罗J·M·斯科特米勒J·N·迪芬德尔费尔
Owner QUALCOMM INC
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