Lead carrier with print formed package components and conductive path redistribution structures

Abstract

A lead carrier includes a temporary support layer, member, medium, or carrier upon which are dispersed a plurality of package sites, organized in a predetermined pattern such as a matrix or array. Each package site within a continuous sheet of mold compound of the lead carrier includes a semiconductor die; a set of terminal structures, each having a top side and an opposing back side that is exposed at a back side of the continuous sheet of mold compound; and a set of electrical current path redistribution structures, each formed as an elongate wiring structure having a first end, a second enddistinct from the first end, a top surface, an opposing bottom surface, a width, and a thickness between its top and bottom surfaces. Each redistribution structure as-fabricated is either electrically pre-coupled to a predetermined terminal structure, or electrically isolated from each terminal structure.

Description

technical field [0001] Aspects of the present disclosure generally relate to lead carriers that package semiconductor dies that can be fabricated at the packaging site. More specifically, aspects of the present disclosure relate to a package site comprising a lead carrier on which a sintered package component is formed and having an interface of surface mount solder joints residing on temporary support layers, components, On a medium or carrier, said temporary support layer, member, medium or carrier can be peeled away from the encapsulation site after the molding process. The package site may include a conductive path redistribution structure therein that is vertically separated or offset from the surface mount interface of the sintered package component. Background technique [0002] The demand for smaller and more portable electronic systems, coupled with the increased integration of today's semiconductor devices, is driving the need for smaller semiconductor packages wi...

AI Technical Summary

Problems solved by technology

The Quad Flat No-Lead (QFN) semiconductor package family is the smallest and most cost-effective semiconductor package product of all semiconductor package types, but when manufactured using conventional technologies and materials, relative to the number of I / O terminals and the electrical power that the technology can support Performance has significant limitations

However, the cost of a double etched leadframe is substantially higher than that of a standard etched leadframe, and the etching and plating process is environmentally undesirable

Images