Phase interpolator and method of implementing a phase interpolator

Abstract

This application describes a phase interpolator implemented in an integrated circuit to generate a clock signal. The phase interpolator includes: a plurality of inputs (121) coupled to receive a plurality of clock signals; a plurality of transistor pairs (330, 332, 340, 342), each transistor pair having a A first transistor at an output node (310) and a second transistor coupled to a second output node (314), wherein a first clock signal associated with the pair of transistors is coupled to a gate of the first transistor and the inverted signal of the first clock signal associated with the pair of transistors is coupled to the gate of the second transistor; a first active inductor load coupled to the first output node (308); and a second active inductor load (312) coupled to the second output node.

Description

technical field [0001] The present application relates generally to integrated circuit devices and, in particular, to phase interpolators and methods of implementing phase interpolators. Background technique [0002] Data transmission is an important function implemented by integrated circuits. A phase interpolator, sometimes called a mixer, is a key component of a clock and data recovery (CDR) circuit. The CDR circuit implements a control loop that can adjust the data sampling clock to sample data at the center of the data eye. The linearity of the phase interpolator is a key indicator to determine the performance of the CDR system. Analog current mode logic (CML) phase interpolators receive differential CML quadrature clocks and mix them together in controlled ratios to generate output clocks with controlled phase offsets relative to the differential CML quadrature clocks. The phase of the output clock can cover a full 360 degree rotation. [0003] The phase interpolat...

AI Technical Summary

Problems solved by technology

However, using passive resistor loads in phase interpolators has a number of disadvantages

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