Three-dimensional integration method of CMOS image sensor

An image sensor, three-dimensional integration technology, applied in the field of three-dimensional integration of CMOS image sensors, can solve the problems of limiting circuit density, difficult to integrate pixel interconnection CMOS image sensors, etc.

CN108666335AInactive Publication Date: 2018-10-16FUDAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2018-10-16
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention belongs to the technical field of semiconductor technology, in particular to a three-dimensional integration method of a CMOS image sensor. The method includes: providing a CMOS image sensor chip fabricated on a fully depleted SOI wafer; forming a first metal interconnection wiring layer and a passivation layer; forming an embedded electrode on the first metal interconnection; cutting the CMOS image sensor chip and performing surface plasma activation processing; and bonding the embedded electrodes of the two CMOS image sensor chips to each other. According to the three-dimensional COMS image sensor, an embedded electrode is used for directly bonding a silicon layer on an insulator to obtain a high-density stacked three-dimensional COMS image sensor without required extra space. The three-dimensional integration method of a CMOS image sensor is suitable for high-density integration.
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Description

technical field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a three-dimensional integration method of a CMOS image sensor. Background technique

[0002] CMOS image sensor three-dimensional integration technology mainly includes through-silicon via (TSV) technology, sequential integration technology and silicon-on-insulator (SOI)-based assembly technology. The interconnection size of TSV technology is generally greater than 5 μm, which is not suitable for high-density integrated circuits with a through hole size of 5 μm or less, and it is difficult to integrate stacked CMOS image sensors with pixel interconnections. Although sequential integration technology, SOI-based assembly technology has the potential to achieve high-density storage, TSVs need to be formed in the outer region of the field-effect transistor, thereby limiting circuit density. Contents of the invention

[0003] In order to solve the above problems, ...

Examples

Embodiment Construction

[0028] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The examples are only used to explain the present invention, not to limit the present invention. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0029] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical" and "horizontal" are based on the orientation or positional relation...