Pipelined analog-to-digit converter comparator offset foreground calibration circuit and method

Abstract

The invention discloses a pipelined analog-to-digit converter comparator offset foreground calibration circuit and method. The circuit comprises a current source I1 and an adjustable resistor string unit array, wherein the adjustable resistor string unit array comprises N adjustable resistor string units RESL1 to RESLN; the current source I1 and the adjustable resistor string units RESL1 to RESLNare connected in series between a power supply VDD and the ground in sequence; the structures of the adjustable resistor string units RESL1 to RESLN are the same, and have adjustable resistance values; and each adjustable resistor string unit comprises 4 fine adjustment resistors R1 to R4, 5 switches SW1 to SW5, 1 two-for-one switch DSW, a comparator COMP, an accumulator ACCU, a threshold value judger THR and a bidirectional shift register SHREG. The pipelined analog-to-digit converter comparator offset foreground calibration circuit disclosed by the invention divides a traditional voltage sharing resistor into four parts so as to finely adjust the offset voltage of a comparator without introducing extra static power consumption, and is particularly applicable to low-power-consumption design.

Description

technical field [0001] The invention relates to the field of integrated circuits, and relates to a circuit and method for calibrating an offset front end of a comparator of a pipeline analog-to-digital converter, and is mainly used in low-power pipeline analog-to-digital converters. Background technique [0002] In the design of a pipelined ADC, the device mismatch due to process deviation and the imbalance of the parasitic inductance and capacitance of the switch will cause the comparator to be out of adjustment, which will seriously affect the performance of the ADC. Generally, the offset can be reduced by increasing the device size, but it will lead to a serious increase in power consumption. Therefore, how to reduce the offset of the comparator without increasing the power consumption is one of the research focuses of the current pipeline ADC design. [0003] The traditional comparator offset calibration mainly adopts the analog method, the offset voltage of the comparat...

AI Technical Summary

Problems solved by technology

[0004] In recent years, many digital calibration methods for comparator offset calibration have appeared, but they mainly focus on solving the static offset error of the comparator, but cannot solve the dynamic offset error of the comparator.

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