Reliability Modeling and Design Guidance for Embryo Hardware Cell Reuse Strategy

A modeling method and reliability technology, applied in computing, special data processing applications, instruments, etc., can solve the problems of model error and inability to reflect the reuse ability, and achieve the effect of improving system repair performance and reducing system reliability

Pending Publication Date: 2019-04-16
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

For a system with both permanent faults and transient faults, or even a higher proportion of transient faults, the model has a large error, and transient fault cells have the characteristics of reusability after self-repair, and the reusability is modeled with permanent faults. cannot be reflected in the model

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  • Reliability Modeling and Design Guidance for Embryo Hardware Cell Reuse Strategy
  • Reliability Modeling and Design Guidance for Embryo Hardware Cell Reuse Strategy
  • Reliability Modeling and Design Guidance for Embryo Hardware Cell Reuse Strategy

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Embodiment Construction

[0043] Below in conjunction with embodiment further set forth this inventive method.

[0044] A reliability modeling and design guidance method for embryonic hardware cell reuse strategies, which aims at the high incidence of transient failures of embryonic hardware in different space environments, and the existing reliability models only reflect permanent failures, and a design method for cell reuse strategies A new reliability model is established, and the optimal design standard is given through reliability analysis, and then the guiding method for determining the optimal design according to the standard is obtained.

[0045] The faults of embryonic electronic hardware can be divided into transient faults and permanent faults, and the current reliability model only reflects permanent faults. To accurately reflect the actual situation of the aerospace environment, it is necessary to add transient fault parameters in the reliability modeling process. Cells with transient fail...

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Abstract

The invention discloses a reliability modeling and design guidance method for an embryo hardware cell reuse strategy, comprising a reliability modeling method oriented to the embryo hardware cell reuse strategy, and a guidance method for realizing an embryo cell array layout optimization design under different spatial environments based on reliability model analysis. The invention regards the reusable fault cells as redundant cells for reliability modeling, and solves the problem that the traditional reliability model can not analyze the influence of the transient fault cells. Based on k-out-of-m model, in which the sum of the number of redundant idle cells and the number of repairable times due to repairable transient failure is expressed by the equivalent total number of idle cells, canbe used to analyze the cell reuse strategy more accurately; According to the fault characteristics of different space environment, the instantaneous fault proportional parameters are calculated, and the reliability comparison of different fault characteristics is realized, which provides a guide standard for optimal selection.

Description

technical field [0001] The invention relates to a reliability modeling and design guidance method for embryo hardware cell reuse strategy, and belongs to the technical field of bionic self-repair hardware design. Background technique [0002] With the rapid development of microelectronics technology and the continuous improvement of semiconductor circuit integration, the feature size of aerospace electronic devices is getting smaller and smaller, and it is easier to cause single event effects. The single event effect refers to a radiation effect that causes abnormal changes in the state of the device when a single high-energy particle passes through the sensitive area of ​​the microelectronic device. It has become the main factor affecting the service life and performance of aerospace electronic systems. The high-energy particles in the space radiation bombard the memory or flip-flop, etc., causing the logic value of the digital circuit to flip, which is called a single even...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 张砦袁霄亮邱尧
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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