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Chip packaging structure

A chip packaging structure and chip technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve problems such as pollution of the environment, and achieve the effect of avoiding environmental pollution and reducing use.

Active Publication Date: 2019-04-30
无锡超钰微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although the plastic encapsulation layer can protect the chip, it will pollute the environment

Method used

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Embodiment Construction

[0093] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0094] see figure 1 , which shows a flowchart of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. The manufacturing method of the chip packaging structure provided by the embodiments of the present invention can be applied to packaging the same or different types of chips. The aforementioned chips are, for example, power transistors, integrated circuit elements, or diodes. The power transistor is, for example, a vertical power transistor, an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) or a bottom-source lateral diffusion MOSFET.

[0095] In step S10 , a wafer is provided, wherein the wafer has a plurality of semiconductor devices. The material tha...

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Abstract

The invention discloses a chip packaging structure. The chip packaging structure can be arranged on a circuit board. The chip packaging structure includes a conductive rack and chips. The conductive rack is provided with a bottom and separating plates protruding from the bottom. The separating plates are electrically connected to the bottom. The chips are arranged on the bottom. The chips and theseparating plates are located on the same side of the bottom. The back side of each chip is provided with an electrode arranged toward the bottom. The electrodes are electrically connected to the bottom. The chip packaging structure is provided with gaps located between the separating plates and the chips.

Description

technical field [0001] The invention relates to a semiconductor packaging process, in particular to a chip packaging structure and a manufacturing method thereof which reduce the use of packaging plastics. Background technique [0002] With the development of portable and wearable electronic products, it has become a trend to develop products with high performance, small size, high speed, high quality and versatility. In order to miniaturize the external dimensions of consumer electronic products, the wafer level chip scale package (Wafer Level Chip Scale Package, WLCSP) process has become a technical means often used in chip packaging. The chip size (CSP) package uses Solder Bump to directly lead out the circuit without using traditional wire bonding. In addition to reducing line resistance, it can also effectively reduce parasitic inductance and increase the operating frequency of the product. In addition, the chip area is close to the package size, and the power density ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L21/48H01L25/07H01L25/18
CPCH01L2224/97H01L2224/73253H01L2224/0603H01L2224/06181
Inventor 谢智正许修文
Owner 无锡超钰微电子有限公司