Slave device and method for serial communication

A serial communication and equipment technology, applied in the field of data communication, can solve the problems of limited transmission rate and small output data establishment time, and achieve the effect of good establishment time and lower frequency ratio

Active Publication Date: 2020-08-11
CHIPONE TECH BEIJINGCO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In a project, the data transmission delay Tb on the PAD / board is fixed, and the larger the data preparation delay Ta, the smaller the output data setup time Tc, which limits the increase in the transmission rate

Method used

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  • Slave device and method for serial communication
  • Slave device and method for serial communication
  • Slave device and method for serial communication

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Embodiment Construction

[0053] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

[0054] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0055] The SPI bus is a full-duplex, synchronous peripheral interface bus, which includes 4 signal lines: active low slave selection line CS, serial clock line (SCLK), master input / slave output data line MISO, master output / slave input data line MOSI. Due to the few signal lines, the protocol is simple, and the relative data rate is high, a large part of the chip integrates the SPI interface. SPI works in a master-slave mode. This mode usually has a master device and one or more slave devices. D...

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PUM

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Abstract

Disclosed is a slave device and method for serial communication, the method comprising: receiving a serial clock signal via a clock signal terminal; receiving data via a data input terminal, the data including a plurality of continuous bit data; and a system clock signal synchronization, shifting the data to obtain bit data; and synchronously with the serial clock signal, latching the bit data, and sending at least a portion of the latched bit data via a data output terminal, wherein the The serial clock signal and the system clock signal respectively have a first clock period and a second clock period, the first clock period being greater than the second clock period. This method shifts the bit data synchronously with the system clock signal, latches and sends the pre-shifted bit data synchronously with the serial clock signal, so that the preparation time for sending data is transferred to before the sending edge, so that the frequency of the system clock / serial clock signal The ratio is lower, which can increase the transmission rate.

Description

technical field [0001] The invention relates to the technical field of data communication, in particular to a slave device and method for serial communication. Background technique [0002] In the prior art, SPI (Serial Peripheral Interface, Serial Peripheral Interface) is a structural block diagram of a commonly used design method for sending data from a device as figure 1 shown. The SPI slave device 100 receives a serial clock signal SCLK via a clock signal terminal SCLK, receives data via a data input terminal MOSI, and transmits data via a data output terminal MISO. The SPI slave device internally uses a system clock (SYSCLK) that is several times higher than the SPI serial clock (SCLK) frequency to synchronize and detect the SPI serial clock signal SCLK edge in the edge detection module 110, also known as the sending edge, that is, the serial The rising edge or falling edge transition of the clock signal SCLK is the sending edge signal obtained. The sending edge sign...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/42
CPCG06F13/42G06F13/4291
Inventor 黄平
Owner CHIPONE TECH BEIJINGCO LTD
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