Slave devices and methods for serial communication

Abstract

Disclosed are a slave device and method for serial communication. The method comprises: receiving a serial clock signal via a clock signal terminal; receiving data via a data input, the data comprising a plurality of consecutive bit data; Synchronizing with a system clock signal, and shifting the data to obtain bit data; wherein the serial clock signal and the system clock signal are synchronizedwith the serial clock signal, the bit data are latched, at least one part of latched bit data are sent through a data output end, the serial clock signal and the system clock signal are respectively provided with a first clock period and a second clock period, and the first clock period is larger than the second clock period. The method synchronizes shift bit data with a system clock signal and synchronously latches and transmits pre-shifted bit data with a serial clock signal, so that the transmission data preparation time is transferred to the position in front of a transmission edge, the frequency ratio of the system clock signal to the serial clock signal is lower, and the transmission rate can be increased.

Description

technical field [0001] The invention relates to the technical field of data communication, in particular to a slave device and method for serial communication. Background technique [0002] In the prior art, SPI (Serial Peripheral Interface, Serial Peripheral Interface) is a structural block diagram of a commonly used design method for sending data from a device as figure 1 shown. The SPI slave device 100 receives a serial clock signal SCLK via a clock signal terminal SCLK, receives data via a data input terminal MOSI, and transmits data via a data output terminal MISO. The SPI slave device internally uses a system clock (SYSCLK) that is several times higher than the SPI serial clock (SCLK) frequency to synchronize and detect the SPI serial clock signal SCLK edge in the edge detection module 110, also known as the sending edge, that is, the serial The rising edge or falling edge transition of the clock signal SCLK is the sending edge signal obtained. The sending edge sign...

AI Technical Summary

Problems solved by technology

In a project, the data transmission delay Tb on the PAD / board is fixed, and the larger the data preparation delay Ta, the smaller the output data setup time Tc, which limits the increase in the transmission rate

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