Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as leakage current, failure to meet MOSFET device performance, short channel effect, etc., to improve device performance, Improve the inverse short channel effect, reduce the effect of junction capacitance and junction leakage

Active Publication Date: 2021-09-03
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it has been found in practice that MOSFET devices with embedded silicon germanium / silicon carbon source-drain structures formed in the prior art are still prone to leakage currents or short channel effects, which still cannot meet the requirements for further improvement in the performance of MOSFET devices

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
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Embodiment Construction

[0049] Please refer to figure 1 , a PMOS transistor comprising a semiconductor substrate 100, a gate stack structure 101 formed on the surface of the semiconductor substrate 100, and an embedded silicon germanium source and drain formed in the semiconductor substrate 100 on both sides of the gate stack structure 101 102, the formation process includes etching the semiconductor substrate 100 on both sides of the gate stack structure 101 to form a "Σ (Sigma)" shaped source-drain groove; The silicon germanium stress layer is epitaxially grown in the groove, or a stress seed layer is first grown, and then the silicon germanium stress layer is epitaxially grown to form the embedded silicon germanium source and drain 102 .

[0050] With the shrinking of the gate length of transistors, such as entering the 28nm technology node, the short channel effect (SCE) and short channel effect (RSCE) become the key restrictive factors for the performance improvement of the above-mentioned PMOS ...

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof. After forming a first stress seed layer in a source-drain groove, at least ion implantation is performed on the surface layer of the first stress seed layer, and then The second stress seed layer is formed on the layer, the first stress seed layer can provide a smoother contact interface for the second stress seed layer, and the ions implanted in the first stress seed layer can control the first stress seed layer at each position on its surface The epitaxial growth rate of the second stress seed layer, so that the second stress seed layer can be controlled to finally form the target shape, so that the channel edge under the gate stack structure produces a shallower junction and stronger channel control, reducing junction capacitance and junction Leakage, thereby improving the short channel effect and the reverse short channel effect, so that it can meet the requirements of device performance improvement.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] After MOSFET devices are scaled down to 45nm, high-K metal gate (HKMG) needs to be used to suppress the defects of higher gate leakage and reduced gate capacitance due to the problem of polysilicon gate depletion. Epitaxial growth of silicon germanium or silicon carbon in the source and drain grooves (PSR / NSR) formed by etching the source and drain regions to form an embedded silicon germanium / silicon carbon source and drain structure (ie e-SiGe / e-SiC) to provide The compressive stress squeezes the channel or provides the tensile stress to stretch the channel, suppress the short channel effect (SCE), improve the carrier mobility, and thus improve the performance of the MOSFET. However, it has been found in practice that MOSFET devices with embedded silicon germanium / ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/08H01L29/423H01L29/78H01L21/336H01L21/28
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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