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Peak and valley detection circuit, a/d converter and integrated circuit

A detection circuit, valley value technology, applied in the measurement of current/voltage, analog/digital conversion, AC/pulse peak measurement, etc., can solve the problem that the peak hold circuit cannot detect the voltage dead time, etc. Effect

Active Publication Date: 2021-04-06
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the conventional method described above, a dead time during which the peak hold circuit cannot detect the peak value of the voltage is generated

Method used

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  • Peak and valley detection circuit, a/d converter and integrated circuit
  • Peak and valley detection circuit, a/d converter and integrated circuit
  • Peak and valley detection circuit, a/d converter and integrated circuit

Examples

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no. 1 approach

[0023] Hereinafter, a first embodiment will be described with reference to the drawings. figure 1 It is a figure which shows the A / D converter of 1st Embodiment.

[0024] The A / D (Analog-to-Digital: analog-to-digital) converter 100 of this embodiment includes a peak-to-bottom detection circuit 200 and an A / D conversion unit 300 . The A / D converter 100 outputs a value obtained by converting the voltage output from the peak-to-bottom detection circuit 200 as an analog signal into a digital value by the A / D conversion unit 300 .

[0025] The peak-to-valley detection circuit 200 of this embodiment includes power supplies 201, 202, current sources 203, 204, a comparator 205, an operational amplifier 206, a control unit 210, capacitors C1, C2, C3, switches SW1, SW2, SW3, SW4, SW5.

[0026] The power supply 201 outputs a power supply voltage that is regarded as a detection target (monitoring target) of a peak value or a bottom value of the peak value detection circuit 200 . In add...

no. 2 approach

[0104] Next, a second embodiment will be described with reference to the drawings. The second embodiment is different from the first embodiment in that four or more capacitors Cn are provided. Therefore, in the following description of the second embodiment, only the points of difference from the first embodiment will be described, and the parts having the same functional configuration as those of the first embodiment will be given the terms used in the description of the first embodiment. The same reference numerals are assigned the same reference numerals, and description thereof will be omitted.

[0105] Figure 8 It is a figure which shows the A / D converter of 2nd Embodiment. The A / D converter 100A of the present embodiment includes a peak-to-bottom detection circuit 200A and an A / D conversion unit 300 .

[0106] The peak-to-bottom detection circuit 200A of this embodiment includes a control unit 210A, power supplies 201, 202, current sources 203, 204, a comparator 205,...

no. 3 approach

[0114] Next, a third embodiment will be described with reference to the drawings. The third embodiment differs from the first embodiment in that it is an integrated circuit equipped with a plurality of peak and valley detection circuits described in the first embodiment. Therefore, in the following description of the third embodiment, differences from the first embodiment will be described, and the parts having the same functional configuration as those of the first embodiment will be given the appended symbols used in the description of the first embodiment. The same reference numerals are assigned to the figures, and descriptions thereof are omitted.

[0115] Figure 9 It is a 1st figure which shows an example of the integrated apparatus of 3rd Embodiment. The integrated circuit 400 of the present embodiment includes a plurality of peak-to-bottom detection circuits 200B- 1 , peak-to-bottom detection circuits 200B- 2 , an A / D conversion unit 300 , and a switching circuit 35...

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Abstract

The present invention provides a peak and valley detection circuit, an A / D converter and an integrated circuit, and its purpose is to suppress the generation of dead time. The peak-to-valley detection circuit has: more than 3 capacitors; a comparator, which compares the voltage of any one of the capacitors with the input voltage; an operational amplifier, which amplifies the voltage of any one of the capacitors A plurality of switches more than three correspond to the plurality of capacitors respectively, so that the plurality of capacitors are respectively connected to any one of the comparator, the operational amplifier, and the supply source of the input voltage; and the control unit generates sequential switching The control signals of the connection destinations of the plurality of capacitors are supplied to each of the plurality of switches so that the connection destinations of the three capacitors among the plurality of capacitors are different.

Description

technical field [0001] The invention relates to a peak and valley detection circuit, an A / D converter and an integrated circuit. Background technique [0002] It is conventionally known to connect an A / D converter after a peak hold circuit having a comparator and a capacitor, and convert the voltage output from the peak hold circuit as an analog value into a digital value by the A / D converter to obtain the voltage. The peak technology. [0003] Patent Document 1: Japanese Patent Application Laid-Open No. 4-31771 [0004] Patent Document 2: Japanese Patent Laid-Open No. 2003-215173 [0005] In the conventional method described above, a dead time occurs during which the peak hold circuit cannot detect the peak value of the voltage. Specifically, the dead time period is a period in which the A / D converter samples the output of the peak hold circuit and a settling period in which the voltage of the reset capacitor after sampling is brought close to the voltage to be detected....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R19/04G01R19/25
CPCG01R19/04G01R19/2503H03K5/1532H03K5/2481H03M1/124H03K5/2472
Inventor 田岛章光
Owner SOCIONEXT INC