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A method of transparently transmitting sdh bus data based on fpga

A technology of transparent transmission and bus, applied in the direction of bus network, data exchange through path configuration, electrical components, etc., can solve problems such as unfavorable signal integrity, PCB wiring business expansion, and many interconnected signal lines, and achieves a debug-friendly solution. Effect

Active Publication Date: 2020-10-30
中国电子科技集団公司第三十四研究所
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Problems solved by technology

[0005] The purpose of the present invention is to solve the problem that there are too many bus interconnection signal lines in the circuit board of the existing SDH network element equipment or between different circuit boards, which is not conducive to signal integrity, PCB wiring, business expansion, etc., and provides an FPGA-based The method of transparently transmitting SDH bus data

Method used

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  • A method of transparently transmitting sdh bus data based on fpga
  • A method of transparently transmitting sdh bus data based on fpga
  • A method of transparently transmitting sdh bus data based on fpga

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Embodiment

[0048] A method for transparently transmitting SDH bus data based on FPGA. This method uses 2 pairs of FPGA differential IO pins, such as image 3 As shown, the two-way transmission of bus data is realized by using SDR technology for 1 channel or using DDR technology for 2 channels. The programmable device FPGA is connected to the TelecomBus bus interface and 200MHz clock. The differential IO of the FPGA is connected to the other through the connector or directly The differential IO connection of FPGA includes the following steps, such as Figure 4 Shown:

[0049] 1) TelecomBus bus -> The processing steps of the differential IO direction are as follows:

[0050] 1-1) First, use the associated 19.44MHz clock of the TelecomBus bus to combine the 8bit data, 1bitJ0J1 signal and 1bit PL signal of the bus into 10bit data, and perform 5b / 6b encoding;

[0051] 1-2) Send the encoded data to the sending buffer;

[0052] 1-3) Read 6bit data from the cache, and use OSERDES to perform parallel / ser...

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Abstract

The invention discloses a method for transparently transmitting SDH bus data based on an FPGA common differential IO. Two pairs of FPGA differential IO pins are used; two-way transmission of bus datais realized for one path by adopting an SDR technology or for two paths by adopting a DDR technology; a programmable device FPGA is connected with a TelecomBus bus interface and a 200MHz clock, the differential IO of one FPGA is connected with the differential IO of the other FPGA through a connector or is directly connected with the differential IO of the other FPGA, according to the method, thecharacteristics that FPGA common differential IO pins are many and differential signals are high in interference resistance are utilized, the defects that in traditional SDH equipment, the number of interconnected bus pins between functional chips is large, PCB wiring is difficult, crosstalk is prone to happening, and expansion is not facilitated are overcome, the channel testing and loopback functions are supported, and debugging is convenient.

Description

Technical field [0001] The invention relates to the technical field of internal signal processing in SDH, in particular to a method for transparently transmitting SDH bus data based on FPGA. Background technique [0002] Synchronous Digital Hierarchy (SDH), as a mature technology, supports high-speed remote transmission of large-capacity data, can access various types of services such as Ethernet, voice, image, etc., and adopts standard international unified technology Standards enable equipment from different manufacturers to be connected to the network, which is very beneficial to networking. Therefore, SDH has a large number of applications in backbone networks and access networks, and is still very important in the entire transmission network. [0003] The SDH system consists of multiple SDH network elements. The network element equipment needs to complete service access mapping, multiplexing / demultiplexing, crossover, overhead processing and pointer processing functions. Tr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/08H04L12/40
CPCH04J3/085H04L12/40
Inventor 张小辉龚华达覃勇白杨
Owner 中国电子科技集団公司第三十四研究所
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