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Method for transparently transmitting SDH bus data based on FPGA common differential IO

A transparent transmission and differential technology, applied in the direction of data exchange through path configuration, bus network, multiplexing communication, etc., can solve the problems of unfavorable signal integrity, PCB wiring business expansion, and many interconnected signal lines, etc., to achieve effective Useful for debugging

Active Publication Date: 2020-04-10
NO 34 RES INST OF CHINA ELECTRONICS TECH GRP
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  • Abstract
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  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to solve the problem that there are too many bus interconnection signal lines in the circuit board of the existing SDH network element equipment or between different circuit boards, which is not conducive to signal integrity, PCB wiring, business expansion, etc., and provides an FPGA-based A method for transparently transmitting SDH bus data with ordinary differential IO

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  • Method for transparently transmitting SDH bus data based on FPGA common differential IO
  • Method for transparently transmitting SDH bus data based on FPGA common differential IO
  • Method for transparently transmitting SDH bus data based on FPGA common differential IO

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Embodiment

[0047] A method for transparently transmitting SDH bus data based on FPGA common differential IO, which uses two pairs of FPGA differential IO pins, such as image 3 As shown, using SDR technology for 1 channel or using DDR technology for 2 channels to realize the bidirectional transmission of bus data, the programmable device FPGA is connected to the TelecomBus bus interface and 200MHz clock, and the differential IO of the FPGA is directly connected to another chip through a connector or The differential IO of the FPGA is connected, including the following steps, such as Figure 4 Shown:

[0048] 1) TelecomBus bus -> differential IO direction processing, the steps are as follows:

[0049] 1-1) First, use the 19.44MHz clock of the TelecomBus bus to combine the 8bit data, 1bit J0J1 signal and 1bit PL signal of the bus into 10bit data, and perform 5b / 6b encoding;

[0050] 1-2) Send the encoded data into the sending buffer;

[0051]1-3) Read 6bit data from the cache, use OSERD...

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Abstract

The invention discloses a method for transparently transmitting SDH bus data based on an FPGA common differential IO. Two pairs of FPGA differential IO pins are used; two-way transmission of bus datais realized for one path by adopting an SDR technology or for two paths by adopting a DDR technology; a programmable device FPGA is connected with a TelecomBus bus interface and a 200MHz clock, the differential IO of one FPGA is connected with the differential IO of the other FPGA through a connector or is directly connected with the differential IO of the other FPGA, according to the method, thecharacteristics that FPGA common differential IO pins are many and differential signals are high in interference resistance are utilized, the defects that in traditional SDH equipment, the number of interconnected bus pins between functional chips is large, PCB wiring is difficult, crosstalk is prone to happening, and expansion is not facilitated are overcome, the channel testing and loopback functions are supported, and debugging is convenient.

Description

technical field [0001] The invention relates to the technical field of internal signal processing in SDH, in particular to a method for transparently transmitting SDH bus data based on FPGA common differential IO. Background technique [0002] As a mature technology, Synchronous Digital Hierarchy (SDH) supports high-speed remote transmission of large-capacity data, can access various types of services such as Ethernet, voice, and image, and adopts standard international unified technology Standards allow devices from different manufacturers to access the network, which is very beneficial to networking. Therefore, SDH has a large number of applications in the backbone network and access network, and is still very important in the entire transmission network. [0003] An SDH system consists of multiple SDH network elements. Network element equipment needs to complete the functions of service access mapping, multiplexing / demultiplexing, crossover, overhead processing and poin...

Claims

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Application Information

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IPC IPC(8): H04J3/08H04L12/40
CPCH04J3/085H04L12/40
Inventor 张小辉龚华达覃勇白杨
Owner NO 34 RES INST OF CHINA ELECTRONICS TECH GRP
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