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Apparatuses and methods for latching redundancy repair addresses at a memory

A technology of memory address and repair address, applied in the field of device and method for latching redundant repair address at memory

Pending Publication Date: 2020-04-17
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Additional redundant memory requires a larger fuse array with a higher number of fuses to store potentially more addresses

Method used

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  • Apparatuses and methods for latching redundancy repair addresses at a memory
  • Apparatuses and methods for latching redundancy repair addresses at a memory
  • Apparatuses and methods for latching redundancy repair addresses at a memory

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Embodiment Construction

[0013] Certain details are set forth below in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention may be practiced without these specific details. Furthermore, specific embodiments of the invention described herein are provided by way of illustration only, and should not be used to limit the scope of the invention to these specific embodiments. In other instances, well-known circuits, control signals, timing protocols and software operations have not been shown in detail in order to avoid unnecessarily obscuring the present invention.

[0014] figure 1 is a block diagram of a memory repair system 100 according to an embodiment of the disclosure. Memory repair system 100 includes repair decode logic and control circuitry 120 and repair planes 140(0)-(1). Repair plane 140 ( 0 ) includes corresponding memory blocks 145 ( 0 ) and repair logic 150 . Repair plane 140 ...

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Abstract

Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with amemory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.

Description

Background technique [0001] Semiconductor memory requires features of high data reliability, high-speed memory access, lower power consumption, and reduced chip size. One way to achieve high data reliability is by introducing a fuse array, which includes multiple fuse sets and multiple redundant decoders corresponding to the multiple fuse sets, for defective cell rows / columns in the memory array Alternate rows / columns of memory cells are provided. An address for a defective memory of the array can be mapped to redundant memory, repairing the memory location at that address. Each fuse set can store an address of a defective cell (defective address). Each redundant address decoder receives a row / column address signal and compares the received row / column address signal with the defect address stored in the fuse. If the received row / column address signal corresponds to a defective address stored in any fuse, then access to the received row / column address is disabled and redunda...

Claims

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Application Information

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IPC IPC(8): G11C29/00G11C29/44
CPCG11C29/765G11C29/785G11C29/72G11C29/78
Inventor C·莫尔扎诺S·艾亚普利迪
Owner MICRON TECH INC