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A data external memory expansion interface

A technology for expanding interfaces and data storage, which is applied in the field of data external storage expansion interfaces, and can solve problems such as poor real-time performance, difficulty and high cost of expansion, and limited expansion capacity

Active Publication Date: 2021-11-26
THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The invention provides a data external storage expansion interface to solve the problem that the existing MCU storage expansion method realizes expansion through the P1 and P3 pins of the single-chip microcomputer or through serial conversion and parallel chip, resulting in very limited expansion capacity or poor real-time performance, and expansion Difficulty and cost

Method used

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  • A data external memory expansion interface

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Embodiment Construction

[0028] In order to make the above objects, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] Embodiments of the present invention disclose a data extension extended interface that applies to an interface circuit of an external memory.

[0030] Refer figure 1 It is a schematic diagram of a data extension extension interface provided by the embodiment of the present invention, a data extension extension interface, including:

[0031] MicroController Unit, MCU, first decoder, second decoder, adder, with door, non-door, delay, data store, and two or more I / O expansion chips ;

[0032] The data line of the microcontroller is connected to the data input of each I / O expand chip;

[0033] The address line of the microcontrol unit connects the input of the first decoder, the output terminal of the first decoder and the control line of the micro...

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PUM

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Abstract

The invention discloses a data external storage expansion interface, wherein the data line of the MCU is connected to the input end of the I / O expansion chip; the address line is connected to the input end of the first decoder, the output end of the decoder and the control device of the MCU The line is connected to the input end of the AND gate, the output end of the AND gate is connected to the input end of the delay, the output end of the delay is connected to the input end of the adder, and connected to the control line of the memory; the output end of the first decoder is connected to the non- The input end of the gate, the output end of the NOT gate is connected to the reset end of the adder; the output end of the adder is connected to the second decoder, and the output end of the decoder is connected to the chip select line of the I / O expansion chip, the first to The output end of the N-1th I / O expansion chip is connected to the address line of the memory, and the output end of the Nth I / O expansion chip is connected to the data line of the memory; the control line of the MCU is connected to the control line of the I / O expansion chip . The invention breaks through the limitation of the address line of the MCU and the capacity limitation of the traditional data storage expansion method, and satisfies the real-time access requirement of super large capacity.

Description

Technical field [0001] The present invention relates to the field of storage technologies, and in particular, to a data extension extension interface. Background technique [0002] With the increasing popularity of computer network communications, the construction of computer data storage capacity is increasingly important. The number of address tubes of the micro control unit (MCU) limits the access capacity of the memory, and the exemplary involves complex protocols and drivers. Therefore, how to further expand the MCU memory to cope with oversized storage needs, become a problem that the storage technology is eager to solve. [0003] The existing MCU storage extension method is roughly divided into two types: one, through the MCU's P1 and P3 pins to extend access capacity, but this method is limited by the number of P1 and P3 ports, and the expanded capacity is very limited. For example, a normal MCS51 single-chip microcomputer can only extend up to 256 * 256 memory in full de...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40G06F13/42
CPCG06F13/4022G06F13/4221
Inventor 焦涌柯正祥后弘毅戚可生陆保国
Owner THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
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