Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium

A technology of resistive memory and operation method, applied in static memory, digital memory information, information storage and other directions, can solve the problems of high error programming operation of unselected cells, inability to read operations of a single or specific multiple devices, etc., to overcome errors. The effect of programming operations, avoiding misprogramming operations, and reducing the probability of misprogramming

Active Publication Date: 2020-08-21
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the selection of the programming voltage in the existing operation scheme still has a high misprogramming operation for unselected cells, which is very unfavorable for the development of

Method used

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  • Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium
  • Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium
  • Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium

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Example

[0044] First embodiment

[0045] The first exemplary embodiment of the present disclosure provides an operating method of a three-dimensional vertical resistive random access memory array. A specific resistive random access memory in the three-dimensional vertical resistive random access memory array is selected as a selected cell for programming operations.

[0046] First combine figure 1 The structure of the three-dimensional vertical resistive random access memory array of this embodiment is introduced.

[0047] The operating method of the present disclosure is applicable to a three-dimensional vertical resistive random access memory array. The three-dimensional vertical resistive random access memory array includes: a laminated structure in which a planar conductor layer and an insulating layer are sequentially stacked; a columnar electrode vertically penetrating the laminated structure; a resistive dielectric layer surrounding the outer periphery of the columnar electrode; The...

Example

[0071] Second embodiment

[0072] In a second exemplary embodiment of the present disclosure, a method for operating a three-dimensional vertical resistive random access memory array is provided. A specific one of the three-dimensional vertical structure resistive random access memory array is selected or is located on the same word line. / Bit line specific multiple resistive random access memory as selected cells for read operations. The read operation method of this embodiment can perform read and write operations on the same device as the programming operation of the first embodiment, or it can be implemented separately with the method of the first embodiment to implement the read operation illustrated in this embodiment separately (Read operation) or separately implement the write operation (program operation) exemplified in the first embodiment.

[0073] Image 6 It is a flowchart of a method for reading a three-dimensional vertical resistive random access memory array accord...

Example

[0094] The third embodiment

[0095] In the third exemplary embodiment of the present disclosure, a three-dimensional vertical resistive random access memory array is provided for performing the above-mentioned operation method.

[0096] For example, as shown in reference 1, the three-dimensional vertical resistive random access memory array of this embodiment includes: a laminated structure in which a planar conductor layer and an insulating layer are sequentially stacked; a columnar electrode vertically penetrating the laminated structure; and a resistive sensor surrounding the periphery of the columnar electrode Dielectric layer; a resistive random access memory comprising a planar conductive layer, a resistive dielectric layer and a columnar electrode formed at the intersection of a laminated structure and a columnar electrode, wherein the planar conductive layer and the columnar electrode respectively serve as the resistive random access memory At the same time, the planar con...

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Abstract

The invention discloses a three-dimensional vertical resistive random access memory array and an operation method and device thereof, equipment and a medium. The operation method comprises the step ofselecting a specific resistive random access memory in the three-dimensional vertical resistive random access memory array as a selected unit to perform programming operation. The programming operation comprises the following steps: respectively and correspondingly applying voltages Vdd, 0 and Von1 to a word line, a bit line and a selection line where a selected unit is located; applying zero voltage to a selection line where a first non-selected unit corresponding to the selected unit and different from the selected unit is located; in the word lines and the bit lines corresponding to the second non-selected units corresponding to the same selection line as the selected units, except the word lines and the bit lines where the selected units are located, applying voltages V1 to the rest word lines, and apllaying voltages V2 to the rest bit lines, wherein the voltages V1 and V2 meet the condition that the voltage drops of all the second non-selected units are smaller than Vdd/2. Duringprogramming operation, misoperation caused by voltage drop of the resistive random access memory and fluctuation of corresponding programming voltage is overcome.

Description

technical field [0001] The present disclosure belongs to the field of semiconductor devices and integrated circuits, and relates to a three-dimensional vertical resistive memory array and its operation method, device, equipment and medium, in particular to a programming operation for reducing misprogramming and energy consumption of a three-dimensional vertical resistive memory array method and a read operation method that can independently read any unit (single or multiple) of the same word line / bit line, a three-dimensional vertical resistive memory array that performs the above operation method, an operating device that applies the above operation method, and also relates to Electronic devices and computer readable storage media. Background technique [0002] With the rapid development and popularization of mobile smart terminals and the Internet of Things, the number of electronic devices has increased dramatically, accompanied by the generation of huge data volumes, whi...

Claims

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Application Information

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IPC IPC(8): G11C13/00
CPCG11C13/0004G11C13/004G11C13/0069Y02D10/00
Inventor 黄鹏冯玉林刘力锋刘晓彦康晋锋
Owner PEKING UNIV
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