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Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium

A technology of resistive memory and operation method, applied in static memory, digital memory information, information storage and other directions, can solve the problems of high error programming operation of unselected cells, inability to read operations of a single or specific multiple devices, etc., to overcome errors. The effect of programming operations, avoiding misprogramming operations, and reducing the probability of misprogramming

Active Publication Date: 2020-08-21
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the selection of the programming voltage in the existing operation scheme still has a high misprogramming operation for unselected cells, which is very unfavorable for the development of high-performance storage and storage-computing integration.
In addition, the existing read operation schemes are all row / column parallel read, and cannot be read for a single or specific multiple devices

Method used

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  • Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium
  • Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium
  • Three-dimensional vertical resistive random access memory array and operation method and device thereof, equipment and medium

Examples

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no. 1 example

[0045] The first exemplary embodiment of the present disclosure provides a method for operating a three-dimensional vertical resistive memory array, in which a specific resistive memory in the three-dimensional vertical resistive memory array is selected as a selected cell for programming operation.

[0046] combine first figure 1 The structure of the three-dimensional vertical resistive memory array of this embodiment is introduced.

[0047] The operation method of the present disclosure is applicable to a three-dimensional vertical resistive memory array. The three-dimensional vertical resistive variable memory array includes: a stacked structure in which planar conductor layers and insulating layers are stacked in sequence; a columnar electrode vertically penetrating the stacked structure; a resistive dielectric layer surrounding the periphery of the columnar electrode; between the stacked structure and the columnar The intersection of the electrodes forms a resistive vari...

no. 2 example

[0072] In the second exemplary embodiment of the present disclosure, a method for operating a three-dimensional vertical resistive memory array is provided, in which a specific resistive memory in the three-dimensional vertical structure resistive memory array or on the same word line is selected A specific plurality of RRAMs on the / bit line are used as selected cells to perform a read operation. The read operation method in this embodiment can perform read and write operations on the same device as the programming operation in the first embodiment, or can be implemented separately from the method in the first embodiment, and the read operation illustrated in this embodiment is implemented separately (read operation) or the write operation (program operation) exemplified in the first embodiment is implemented separately.

[0073] Figure 6 It is a flowchart of a read operation method of a three-dimensional vertical resistive memory array according to an embodiment of the pre...

no. 3 example

[0095] In a third exemplary embodiment of the present disclosure, a three-dimensional vertical resistive memory array is provided for performing the above operation method.

[0096] For example, as shown in reference 1, the three-dimensional vertical resistive variable memory array of this embodiment includes: a laminated structure in which planar conductor layers and insulating layers are stacked in sequence; columnar electrodes vertically penetrating through the laminated structure; resistive variable memory arrays surrounding the columnar electrodes Dielectric layer; a resistive variable memory comprising a planar conductor layer, a resistive dielectric layer and a columnar electrode formed at the intersection of the stacked structure and the columnar electrode, wherein the planar conductor layer and the columnar electrode are respectively used as the resistive variable memory The two electrodes of the two electrodes; at the same time, the planar conductor layer is used as a...

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Abstract

The invention discloses a three-dimensional vertical resistive random access memory array and an operation method and device thereof, equipment and a medium. The operation method comprises the step ofselecting a specific resistive random access memory in the three-dimensional vertical resistive random access memory array as a selected unit to perform programming operation. The programming operation comprises the following steps: respectively and correspondingly applying voltages Vdd, 0 and Von1 to a word line, a bit line and a selection line where a selected unit is located; applying zero voltage to a selection line where a first non-selected unit corresponding to the selected unit and different from the selected unit is located; in the word lines and the bit lines corresponding to the second non-selected units corresponding to the same selection line as the selected units, except the word lines and the bit lines where the selected units are located, applying voltages V1 to the rest word lines, and apllaying voltages V2 to the rest bit lines, wherein the voltages V1 and V2 meet the condition that the voltage drops of all the second non-selected units are smaller than Vdd / 2. Duringprogramming operation, misoperation caused by voltage drop of the resistive random access memory and fluctuation of corresponding programming voltage is overcome.

Description

technical field [0001] The present disclosure belongs to the field of semiconductor devices and integrated circuits, and relates to a three-dimensional vertical resistive memory array and its operation method, device, equipment and medium, in particular to a programming operation for reducing misprogramming and energy consumption of a three-dimensional vertical resistive memory array method and a read operation method that can independently read any unit (single or multiple) of the same word line / bit line, a three-dimensional vertical resistive memory array that performs the above operation method, an operating device that applies the above operation method, and also relates to Electronic devices and computer readable storage media. Background technique [0002] With the rapid development and popularization of mobile smart terminals and the Internet of Things, the number of electronic devices has increased dramatically, accompanied by the generation of huge data volumes, whi...

Claims

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Application Information

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IPC IPC(8): G11C13/00
CPCG11C13/0004G11C13/004G11C13/0069Y02D10/00
Inventor 黄鹏冯玉林刘力锋刘晓彦康晋锋
Owner PEKING UNIV
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