An efficient ddr access method

Abstract

The invention discloses an efficient DDR access method and application, comprising: a FIFO controller determines whether a current operation on a DDR memory is a write operation or a read operation according to read data c_fifo_rdata of a control interface FIFO, and when a write operation is performed on the DDR memory, the FIFO The controller sends the read data c_fifo_rdata and write data FIFO of the control interface FIFO to the DDR controller based on APP_CMD, and the DDR controller based on APP_CMD realizes data interaction with the DDR memory. When the DDR memory is read, the FIFO controller will control the The read data c_fifo_rdata of the interface FIFO is sent to the DDR controller based on APP_CMD, and the data read from the DDR memory is sent to the read data FIFO for data buffering, which improves the access efficiency of the DDR memory.

Description

technical field [0001] The invention relates to DDR (Double Data Rate SDRAM, double data rate synchronous dynamic memory) access, in particular to an efficient DDR access method. Background technique [0002] DDR is a widely used memory. It allows data access on the rising and falling edges of the clock. Its speed is twice that of SDRAM at the same frequency. It is often used in systems with large data throughput and high speed. . The DDR controller is actually a bridge for data transmission between the user terminal and the DDR memory. Through the DDR controller, the user terminal commands are converted into the command format supported by the DDR memory, so that the user terminal can access the DDR. [0003] However, DDR read and write needs to follow specific operations: when writing data, you must check whether app_rdy (DDR core ready signal) and app_wdf_rdy (DDR write FIFO ready signal) are valid at the same time, otherwise the write command cannot be successfully writ...

AI Technical Summary

Problems solved by technology

If the signals related to reading and writing data of DDR memory cannot be guaranteed to be valid at the same clock, data reading and writing may fail, which will greatly reduce the efficiency of DDR access

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