Multi-thread integrated control method and device

Abstract

The invention discloses a control method and device for multi-thread synthesis. Logic device; if so, split all logic devices of the target type into multiple logic device groups according to the determined device grouping parameters; when it is necessary to perform logic synthesis on all logic devices of the target type, start the All child threads created perform logic synthesis operations on all groups of logic devices in parallel. It can be seen that the present invention can divide the logic devices included in the original netlist into multiple logic device groups and perform parallel logic synthesis when there are logic devices that need to be split, which is beneficial to reduce the logic synthesis time and improve the logic synthesis efficiency , and can also improve the utilization of CPU processing resources.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a multi-thread synthesis control method and device. Background technique [0002] In the FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) design process, relevant personnel need to use EDA development tools to perform logic synthesis operations on RTL design files written in Verilog or VHDL language, in order to complete the RTL design files to synthesis Post-netlist conversion. Among them, performing logic synthesis operations on RTL design files mainly includes processing processes such as analysis of RTL design files, logic synthesis, logic derivation, and logic mapping. The processing objects of each processing flow generally include non-sequential devices such as basic logic gates, sequential devices, Memory, logical operation unit, etc. [0003] However, practice has found that in the face of RTL design files with complex and changeable structures, there ...

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Problems solved by technology

[0003] However, practice has found that in the face of RTL design files with complex and changeable structures, there will be some special logic devices in the RTL design files, and the execution time will be longer when processing such special logic devices. For example: there are A certain type of logic device accounts for a relatively large number of all logic devices, that is, the distribution of device resources is extremely unbalanced, which makes the execution time of processing this type of logic device longer, resulting in low logic synthesis efficiency.

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