Realization Control Method and Device of Logic Synthesis
A technology of logic synthesis and control method, which is applied in the field of FPGA, can solve the problems of affecting logic synthesis efficiency and increasing execution time, and achieve the effect of improving logic synthesis efficiency, increasing utilization rate, and improving user experience
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Embodiment 1
[0054] see figure 1 , figure 1 It is a schematic flowchart of a logic synthesis implementation control method disclosed in the embodiment of the present invention. in, figure 1 The described method can be applied to an FPGA logic synthesis tool, which is not limited in the embodiment of the present invention. Such as figure 1 As shown, the method may include the following operations:
[0055] 101. The FPGA logic synthesis tool determines a processing flow group satisfying preset parallel processing conditions from the logic synthesis flow corresponding to the target RTL design file.
[0056] In the embodiment of the present invention, the processing flow group includes at least two processing flows that can be processed in parallel, that is, for a processing flow group, it includes two or more processing flows and all the processing flows it includes are capable of parallel execution. And the target RTL design file is any RTL design file read by the FPGA logic synthesis ...
Embodiment 2
[0065] see figure 2 , figure 2 It is a schematic flow chart of another logic synthesis implementation control method disclosed in the embodiment of the present invention. in, figure 2 The described method can be applied to an FPGA logic synthesis tool, which is not limited in the embodiment of the present invention. Such as figure 2 As shown, the method may include the following operations:
[0066] 201. The FPGA logic synthesis tool determines all first-level processing flows and all second-level processing flows included in each first-level processing flow from the logic synthesis flow corresponding to the target RTL design file.
[0067]In the embodiment of the present invention, after all the first-level processing flows are determined, step 202 may be executed for each first-level processing flow. It should be noted that all the secondary processing flows included in each primary processing flow can be understood as all the sub-flows included in each primary proc...
Embodiment 3
[0107] see Figure 4 , Figure 4 It is a structural schematic diagram of a logical synthesis realization control device disclosed in the embodiment of the present invention. in, Figure 4 The described device can be applied to an FPGA logic synthesis tool, which is not limited in the embodiment of the present invention. Such as Figure 4 As shown, the device may include:
[0108] The first determining module 301 is configured to determine a processing flow group that satisfies preset parallel processing conditions from the logic synthesis flow corresponding to the target RTL design file, the processing flow group includes at least two processing flows that can be processed in parallel, and the target RTL design The file is any RTL design file or any RTL design file that meets the preset file conditions.
[0109] The multi-thread parallel module 302 is used to start all sub-threads created in advance for all the processing flows included in the processing flow group to exe...
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