Multi-thread comprehensive control method and device

Abstract

The invention discloses a multi-thread comprehensive control method and device, and the method comprises the steps: judging whether there is a logic device of a target type meeting a preset device grouping condition in all types of logic devices included in an original netlist or not after an RTL design file is analyzed to obtain the original netlist; if so, splitting all logic devices of the target type into a plurality of logic device groups according to the determined device grouping parameters; and when logic synthesis needs to be performed on all the logic devices of the target type, starting all sub-threads created for all the logic device groups in advance to execute logic synthesis operation on all the logic device groups in parallel. Visibly, when the logic devices needing to be split exist in the logic devices included in the original netlist, the logic devices can be split into the multiple logic device groups and subjected to parallel logic synthesis, the logic synthesis time can be shortened, the logic synthesis efficiency can be improved, and the utilization rate of CPU processing resources can be increased.

Description

Technical field[0001]The present invention relates to the field of FPGA, and more particularly to a multi-threaded synthetic control method and device.Background technique[0002]In the design process of FPGA (Field-Programmable Gate Array, Field Programmable Door Array), the relevant personnel need to perform logical integrated operations using the EDA development tool to perform logical integrated operations to complete the RTL design file to complete the RTL design file. Transformation of the rear network table. Among them, the logical integrated operation of the RTL design file mainly includes the resolution, logical integration, logical derivation, logical mapping of the RTL design file, and processing objects for each processing process generally include non-timing devices, timing devices such as basic logic gates. Memory, logical operation unit, etc.[0003]However, practical discovery, facing the structure of complex and variable RTL design files, there are some special logic de...

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Problems solved by technology

[0003] However, practice has found that in the face of RTL design files with complex and changeable structures, there will be some special logic devices in the RTL design files, and the execution time will be longer when processing such special logic devices. For example: there are A certain type of logic device accounts for a relatively large number of all logic devices, that is, the distribution of device resources is extremely unbalanced, which makes the execution time of processing this type of logic device longer, resulting in low logic synthesis efficiency.

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