Logic comprehensive control method and device

A logic synthesis and control method technology, applied in the FPGA field, can solve problems such as reducing development efficiency and increasing development time

Active Publication Date: 2021-03-23
GOWIN SEMICON CORP LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Practice has found that every time the parameters of the system algorithm are modified, the entire process of FPGA develo...

Method used

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  • Logic comprehensive control method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0060] see figure 1 , figure 1 It is a schematic flowchart of a logic synthesis control method disclosed in an embodiment of the present invention. in, figure 1 The described method can be applied to an FPGA synthesis tool, and the FPGA synthesis tool can be combined with artificial intelligence to realize the application of FPGA in the field of artificial intelligence. Such as figure 1 As shown, the method may include the following operations:

[0061] 101. Whether the initial value of the memory in the read RTL design file detected by the FPGA synthesis tool changes; when the judgment result of step 101 is yes, trigger execution of step 102; when the judgment result of step 101 is no, this program can be ended The sub-process can also continue to trigger the execution of step 101.

[0062] In the embodiment of the present invention, in the development and design process of FPGA, the memory (memory) defined in the RTL design file will usually be inferred (infer) as the m...

Embodiment 2

[0084] see figure 2 , figure 2 It is a schematic flowchart of another logic synthesis control method disclosed in the embodiment of the present invention. in, figure 2 The described method can be applied to an FPGA synthesis tool, and the FPGA synthesis tool can be combined with artificial intelligence to realize the application of FPGA in the field of artificial intelligence. Such as figure 2 As shown, the method may include the following operations:

[0085] 201. After the logic synthesis operation is performed on the read RTL design file for the first time, the FPGA synthesis tool establishes the initial value of the memory in the RTL design file and the memory instance in the post-synthesis netlist obtained by performing the logic synthesis operation on the RTL design file last time The mapping relationship between the initial values ​​of .

[0086] Wherein, in step 201, the latest logic synthesis operation performed on the RTL design file is the first logic synth...

Embodiment 3

[0102] see Figure 4 , Figure 4 It is a structural schematic diagram of a logic synthesis control device disclosed in an embodiment of the present invention. in, Figure 4 The described device can be applied in an FPGA synthesis tool, and the FPGA synthesis tool can be combined with artificial intelligence to realize the application of FPGA in the field of artificial intelligence. Such as Figure 4 As shown, the logic synthesis control device may include:

[0103] The first detection module 301 is configured to detect whether the initial value of the memory in the read RTL design file has changed.

[0104] The modification module 302 is used to modify the netlist after the synthesis obtained by performing the logic synthesis operation on the RTL design file last time according to the pre-established mapping relationship when the first detection module 301 detects that the initial value of the memory in the RTL design file changes. The initial value of the memory instance...

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Abstract

The invention discloses a logic comprehensive control method and device. The logic comprehensive control method comprises the steps of detecting whether an initial value of a memory in a read RTL design file is changed or not; when the detection result is yes, according to a pre-established mapping relationship, correspondingly modifying an initial value of a memory instance in a synthesized netlist obtained by executing logic synthesis operation on the RTL design file most recently so as to update the synthesized netlist, wherein the mapping relationship is used for representing a corresponding relationship between the initial value of the memory in the RTL design file and the initial value of the memory instance in the synthesized netlist obtained by performing logic synthesis operationon the RTL design file last time. Obviously, according to the method, under the condition that the initial value of the memory in the RTL design file is changed, only the initial value of the memory instance in the synthesized netlist needs to be correspondingly modified according to the pre-established mapping relation, logic synthesis does not need to be carried out again, logic synthesis time can be shortened, and the development and design efficiency of the FPGA is improved.

Description

technical field [0001] The invention relates to the field of FPGA technology, in particular to a logic synthesis control method and device. Background technique [0002] Artificial intelligence is a new technical science that studies and develops theories, methods, technologies and application systems for simulating, extending and expanding human intelligence. It is the core driving force of a new round of industrial transformation and a new engine of economic development. As a general-purpose programmable logic device, FPGA is designed closer to the underlying hardware architecture, has a large number of RAM resources, DSP resources, etc., is good at data parallel computing, more flexible and low-latency, and also has power consumption. Low cost, programmable and flexible design. Based on this, FPGA has been widely used in many application fields of artificial intelligence. [0003] In the practical application of applying FPGA to the field of artificial intelligence, aft...

Claims

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Application Information

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IPC IPC(8): G06F30/327G06F30/343
CPCG06F30/327G06F30/343
Inventor 王宁刘奎张青刘锴
Owner GOWIN SEMICON CORP LTD
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