Convolutional neural network back propagation mapping method based on cyclic recombination and blocking

Abstract

The invention discloses a convolutional neural network back propagation mapping method based on cyclic recombination and blocking, is suitable for an on-chip neural network training accelerator circuit, and belongs to the field of neural network accelerators. According to the method, a back propagation algorithm in neural network training is mapped to an existing neural network accelerator engine used for forward reasoning in a data scheduling mode, namely, large convolution operation in back propagation of a convolutional neural network is remapped; thus, the scale and dimension of the convolution can be adapted to a neural network accelerator for forward reasoning. According to the method, under the condition that a hardware architecture hardly needs to be changed, a specific large convolution operation of a back propagation algorithm is recombined and partitioned and is mapped to an existing neural network accelerator engine for forward reasoning; therefore, the accelerator which can only carry out forward reasoning originally can be easily adaptive to a back propagation algorithm, and then neural network training is carried out on a chip.

Description

technical field [0001] The invention belongs to the field of neural network accelerators, especially for on-chip retraining, and is used to adapt the backpropagation algorithm to the neural network accelerator that can only perform forward reasoning, so as to realize the training of the neural network on the chip without requiring Deploy after training on the server side. Background technique [0002] On-chip training refers to the process of retraining the neural network deployed on the neural network accelerator chip through a specific method. Traditional neural network accelerator chips usually need to train the model with big data through the server side, and then deploy it to the chip through the interface for forward reasoning. Therefore, neural network accelerator chips generally used for edge devices can only perform inference tasks and cannot perform training tasks. [0003] In recent years, the problem of user privacy leakage has become more and more serious. As...

AI Technical Summary

Problems solved by technology

[0004] There are only a few neural network chips that support on-chip training. The biggest difficulty is that the training task requires a larger amount of computation and storage than forward inference. These two resources are very scarce in edge devices.

In addition, the internal data flow of different neural network accelerator chips is different. When performing reverse reasoning tasks, the corresponding software needs to map tasks for different accelerator architectures, which increases the difficulty of designing supporting software.

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