Communication clock reset signal processing circuit and method

Abstract

A communication clock reset signal processing circuit of the present invention includes a communication clock domain reset signal generation unit, a synchronization unit and a sampling unit, the communication clock domain reset signal generation unit generates a communication clock reset signal according to the main reset signal, and the synchronization unit generates the communication clock reset signal Synchronized from the communication clock domain to the main clock domain, the sampling unit samples the synchronized communication clock reset signal to determine whether the communication clock reset signal has been released. If the communication clock reset signal has not been released, a release signal is generated in the main clock domain to release the communication clock reset signal. Therefore, when there is no communication clock after power-on, it is safe to use the signal of the main clock domain to release the reset signal of the communication clock domain, and if there is a communication clock after power-on, use the communication clock to release the reset signal. In this way, when it is impossible to predict whether the user will give the communication clock after power-on, the chip can be safely placed in a state where it can communicate at any time.

Description

technical field [0001] The present invention relates to the technical field of circuits, and more particularly, to a communication clock reset signal processing circuit and method. Background technique [0002] In digital chip design, all registers will have an asynchronous reset signal, which is used to assign initial values ​​to the registers when they are powered on. In order to ensure that the asynchronous reset signal does not violate the corresponding timing requirements (recovery time, removal time), the actual circuit will use the reset bridge to process the original reset signal, so that the processed reset signal can meet the timing requirements when released. [0003] In applications that actually need to communicate with external devices using the SPI interface, there are usually two clocks, a main clock signal CLK_MAIN and a clock signal CLK_SPI responsible for communication. The main clock CLK_MAIN starts to work after it is powered on. After the reset signal ...

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Problems solved by technology

In addition, the communication clock signal CLK_SPI may only be sent for a period of time during data communication. Although all registers corresponding to CLK_SPI can also get an initial value when the reset signal arrives after power-on, if the user does not to CLK_SPI, then the reset signal of the corresponding register can only be released when the user sends CLK_SPI for communication, which will inevitably cause an error in the first data communication after power-on

[0004] In view of this situation, in the prior art, the user sends at least two clock pulses to release the reset signal before communicating, but this may cause additional burden to the user

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