Three-dimensional memory device and manufacturing method thereof
A memory and three-dimensional technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of reduced integration and increased quantity
Pending Publication Date: 2022-04-22
SK HYNIX INC
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- Application Information
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Problems solved by technology
However, if the number of word lines is increased, the number of wirings required to connect the word lines and row decoders increases, and therefore, the degree of integration may decrease
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[0024] Advantages and features of the present disclosure, and methods of achieving them will become apparent from the description of exemplary embodiments herein below described with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.
[0025] Since figures, dimensions, ratios, angles, numbers of elements given in the drawings describing the embodiments of the present disclosure are merely exemplary, the present disclosure is not limited to the illustrated matters. Throughout the specification, like reference numerals refer to like components. In describing the present disclosure, when it is determined that the detailed description of related art may obscure the gist or clarity of the present disclosure, its detailed description will ...
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The invention relates to a three-dimensional memory device and a manufacturing method thereof. A three-dimensional memory device includes a lower stack and an upper stack, the lower stack and the upper stack being stacked on each other and each including a plurality of word lines alternately stacked with a plurality of interlayer dielectric layers, each of the lower laminate and the upper laminate includes a first cell portion, a second cell portion, a coupling portion coupling the first cell portion and the second cell portion, and a step portion extending parallel to the coupling portion from the first cell portion, in which a pad region of the word line is disposed in a step-like manner, and wherein the pad region of the word line is disposed in the step-like manner. The coupling portion of the upper laminate is disposed to overlap with the stepped portion of the lower laminate, and the stepped portion of the upper laminate is disposed to overlap with the coupling portion of the lower laminate.
Description
technical field [0001] The various embodiments relate generally to semiconductor technology, and more particularly to three-dimensional memory devices and methods of manufacturing the same. Background technique [0002] The advantage of a three-dimensional memory device is that by stacking memory cells in the vertical direction to increase the number of stacks, a larger capacity can be achieved in the same area, providing higher performance and excellent power efficiency. [0003] In a three-dimensional memory device, integration can be increased by increasing the number of word lines to be stacked. However, if the number of word lines is increased, the number of wirings required to connect the word lines and row decoders increases, and thus, the degree of integration may decrease. Therefore, there is a need for an efficient wiring layout method. Contents of the invention [0004] Various embodiments relate to three-dimensional memory devices with improved integration an...
Claims
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IPC IPC(8): H01L27/11521H01L27/11556H01L27/11568H01L27/11582
CPCH10B41/27H10B43/30H10B41/30H10B43/27H10B41/10H10B41/50H10B41/40H10B43/10H10B43/50H10B43/40H01L21/76877H10B41/35H10B43/35H01L23/5226H10B41/46
Inventor 吴星来
Owner SK HYNIX INC