Decoding method for simulating decoding circuit stop criterion based on probability calculation
A technology of analog decoding and probability calculation, which is applied in the direction of error detection coding, coding, and code conversion of multiple parity bits, and can solve the problem of reducing circuit implementation complexity and dynamic power consumption, high circuit implementation complexity, The system handles problems such as high delay to achieve the effect of improving system throughput, having universal applicability, and reducing implementation complexity
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[0064] In order to make the above-mentioned objects, features and advantages of the present invention easier to understand, it will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. A kind of LDPC decoding method based on the analog decoding circuit stop criterion of probability calculation, the system parameters in the present embodiment are as shown in the following table:
[0065] parameter Details Symbols per frame 512 code rate 1 / 2 Punching method Check digit last 256 bits Modulation BPSK channel model Gaussian white noise The maximum number of iterations of the decoder 100
[0066] like figure 1As shown, the specific implementation steps of this embodiment are as follows:
[0067] In step 1, a factor graph model is established for the LDPC analog decoding circuit.
[0068] According to the check matrix H judge A factor graph model G=(VNs∪CNs,Ξ) with check ...
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