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Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line

An instruction cache, branch target address technology, applied in memory address/allocation/relocation, electrical digital data processing, memory systems, etc., can solve problems such as complex situations, avoid branch loss, and improve branch performance.

Inactive Publication Date: 2006-08-16
IP FIRST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, the situation is complicated by the fact that variable-length instructions are executed in the processor, so branch instructions may span two cache lines

Method used

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  • Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line
  • Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line
  • Device and method of branch for processing branch goal address high speed area covering crossed instruction high speed line

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Experimental program
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Embodiment Construction

[0054] now refer to figure 1 , which is a block diagram of a microprocessor 100 with a pipeline according to the present invention. Microprocessor 100 includes a number of stages from 101 to 132 . In one embodiment, the microprocessor 100 includes an x86 architecture processor.

[0055] The first stage of the pipeline processor 100 is the instruction cache generation stage or C stage 101 for short. The C-stage 101 generates the fetch address 162 used to select a cache line in the instruction cache 202 (see FIG. 2).

[0056] The next stage is the I stage 102, or the instruction fetch stage. In order to fetch instructions to the pipeline processor 100 for execution, the I stage 102 provides the stage for the pipeline processor 100 to fetch the address 162 to the instruction cache 202 (see FIG. 2 ). The instruction cache 202 will be described in more detail with reference to FIG. 2 . In one embodiment, the instruction cache 202 is a two-cycle cache. Stage B 104 is the secon...

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Abstract

A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

Description

technical field [0001] The present invention is in the field of branch target address caches in microprocessors, and more particularly to a branch instruction that covers spanning instruction cache lines. Background technique [0002] A microprocessor includes multiple pipeline stages, and each stage fulfills different functional requirements in the execution of program instructions. The functions of the pipeline stages are usually instruction fetch, instruction decode, instruction execution, memory access and result write-back. [0003] The instruction fetch phase is to fetch the next instruction in the currently executing program. The next instruction is typically the instruction with the next consecutive memory address. However, as far as the branch instruction is taken, the next instruction is the instruction of the memory address specified by the branch instruction, which is usually used as a reference of the branch target address. The instruction fetch stage is to f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/42G06F12/02G06F9/00
Inventor 布兰特比恩G·葛兰亨利汤玛斯C·麦当劳
Owner IP FIRST