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Code generation circuit

A code generation and circuit technology, applied in the field of code generation circuits, can solve problems such as non-existence and reduction of division time

Inactive Publication Date: 2003-08-27
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] Although efforts have been made to reduce the division time in the code generation circuit, such as reducing the total operation time by parallel operation, there is no general method to reduce the division time by utilizing the characteristics of the encoded target data to be input

Method used

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Embodiment Construction

[0036] Embodiments of the present invention will be described with reference to the drawings.

[0037] FIG. 1 is a circuit diagram showing a code generating circuit according to a first embodiment of the present invention. In FIG. 1, F1 to F8 represent flip-flops configured as shift registers, 101 represents a division remainder determination circuit, 101 to 113 represent exclusive OR circuits, and 130 to 137 represent circuits for selecting the flip-flop output or division remainder determination A selection circuit output by 101, 140 represents a control signal from the division remainder determination circuit 101, and 150 represents a signal for inputting input data structure information from the outside. The generator polynomial in this circuit is G(X)=X^8+X^6+X^5+X^3+1.

[0038]In the code generation circuit configured as shown in FIG. 1, the division remainder decision circuit 101 detects the first 0-digit number of values ​​of the shift register or flip-flops F8 to F1,...

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Abstract

A code generator circuit according to the invention comprises a divider circuit configured as a shift register where flip-flops F1-F8, selectors 130-137, and exclusive-OR circuits 110, 111, 112, 113 are serially connected, and a division remainder decision circuit 101 including a remainder shift circuit that compares the number of digits of leading 0s of the value on the shift register with the number of leading 0s of the subsequent input data and assumes the number of digits of the smaller as the number of skip digits, then outputs the value on the shift register shifted by the number of skip digits, characterized in that the selector circuits select the output of the remainder shift circuit when the number of skip digits is 1 or more and select the output of the flip-flops connected immediately before the respective selector circuits when the number of skip digits is 0.

Description

technical field [0001] The present invention relates to a code generation circuit for generating cyclic codes using a generator polynomial. Background technique [0002] Cyclic codes generated by using generator polynomials have undergone extensive research and technical development. Various codes are used in a wide variety of applications such as telecommunications and digital media recording. [0003] By using the polynomial of Galois field (Galois field) GF(2), let the b-degree generator polynomial be G(X), and the polynomial that uses a-bit encoded target data as a coefficient is I(X), and I(X) is divided by The quotient obtained by G(X) is Q(X), and the remainder is R(X), then the operation is expressed as I(X)X^b=Q(X)G(X)+R(X), where , omit the multiplication sign and set ^ to be the exponentiation sign. [0004] I(X)X^b+R(X) is a code word of a cyclic code generated from encoding target data, and is composed of a bit of encoding target data combined with b bits of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10H03M13/15
CPCH03M13/15
Inventor 关口启之
Owner PANASONIC CORP