NOR structure semiconductor memory

Abstract

The invention is a kind of semiconductor memorizing device which has NOR structure of novel bit line connection configuration, it includes a semiconductor memorizing unit array which is connected to several bit lines by electricity. The bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main line through at least two bit line transistors. The bit lines of the NOR structure semiconductor memorizing device is arranged to that the four adjoining bit lines are selected from four different bit line groups and coupled to four different main bit lines. In programming or reading operation, a programming voltage or sensing current supply two of the four adjoining bit lines, the other two bit lines connect to the ground.

Description

technical field [0001] The invention relates to a semiconductor memory device, in particular to a NOR structure semiconductor memory device with a novel bit line connection configuration. Background technique [0002] figure 1 It is a schematic diagram showing a conventional NOR structure semiconductor memory device 1 . To simplify the description, figure 1 The shown conventional NOR structure memory device 1 includes a 2×8 memory cell array, and the memory cells are electrically connected to corresponding word lines and bit lines. More precisely, the memory cells arranged in a column are electrically connected to a word line in parallel, and the memory cells arranged in a row are electrically connected in parallel to two adjacent bit lines. For example, the memory cells M10 to M17 are arranged such that their gates are electrically connected to a word line WL1 in parallel. The memory cells M10 and M00 are arranged such that their channel electrodes (ie, source and drain...

AI Technical Summary

Problems solved by technology

However, during the data read operation of the memory cell M00, due to the leakage current paths L2 and L3 caused by the simultaneous activation of the memory cells M01, M02, M03, and M04 by the word line WL0, it takes much time to increase the potential of the main bit line MBL2. time growth

In other words, figure 1 The existing NOR structure semiconductor device shown is difficult to achieve high-speed data readout operation

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