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Interrupt controller for microprocessor

A technology of microprocessors and controllers, used in program control design, electrical digital data processing, instrumentation, etc., to solve problems such as loss of unprocessed events

Inactive Publication Date: 2004-09-22
THOMSON LICENSING SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method may also lose unhandled events if the state of the group was changed by a new event during the read or between the read and reset

Method used

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  • Interrupt controller for microprocessor
  • Interrupt controller for microprocessor
  • Interrupt controller for microprocessor

Examples

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Embodiment Construction

[0071] In the figures, identical circuit elements and signals are provided with standard reference numerals.

[0072] known in the prior art, figure 1 The illustrated interrupt controller for microprocessor 30 in this case includes, for example, two event memories 40 and 41 which are combined to form a group. Each event memory 40 and 41 has an input for a setup signal 5, an input for a data clock signal 13 and a data input signal 14, an input for describing the state of the respective event memory 40 or 41 Output for Event Memory Signal 4. The set signal 5 of an event memory 40 or 41 becomes active when the appropriate edge detection block 50 detects the activation of the event signal associated with this event memory 40 or 41 . In this case, an event pulse signal 7 is generated as a set signal 5 from the edge detection block 50 to the event memory 40 or 41 . Arranged downstream of each event memory 40 and 41 is a corresponding interrupt enable section in the form of a log...

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Abstract

An interrupt controller for a microprocessor (30) having a plurality of event memories (40, 41) which are combined to form at least one group and each have an input for a setting signal (5) and an output for an event memory signal (4) which portrays the state of the event memory (40, 41),- where the setting signal (5) for an event memory (40, 41) becomes active when activation of an event signal (8) associated with this event memory (40, 41) is detected, - where the event memory signals (4) are connected to an interrupt signal (9) for the microprocessor (30), - where the microprocessor (30) has read and write access to the event memory signals (4) via a data bus (10), and - where the event memories (40, 41) each have an input for a resetting signal (3), is designed such that the event memories can be specifically altered individually or else in groups without events being unintentionally lost in the process, which means that they cannot be processed. To this end, the resetting signal (3) for an event memory (40, 41) in a group becomes active when the microprocessor (30) effects write access to the group containing this event memory (40, 41) using a first write signal (15) and, at the same time, that individual signal (16) from the microprocessor (30) which is associated with this event memory (40, 41) is active on the data bus (10).

Description

technical field [0001] The invention relates to an interrupt controller for a microprocessor having a plurality of event memories combined to form at least one set and each event memory having an input for a set signal and an output for an event memory signal describing the state of the event memory, wherein the set signal for the event memory becomes active when the activation of the event signal associated with this event memory is detected, wherein the event memory signals are connected to interrupt signals for the microprocessor, wherein the microprocessor has read and write access to the event memory signals via a data bus, and wherein each event memory has an input for a reset signal. Background technique [0002] This interrupt controller is intended to be used eg in a device for recording or reproducing information on an optical information medium. [0003] When certain events occur, the interrupt controller interrupts program execution in the microprocessor so that...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48
CPCG06F9/4812G06F9/48
Inventor 鲁迪格·布伦海姆
Owner THOMSON LICENSING SA