Memory control apparatus and method for scheduling commands

A technology of memory controller and control method, applied in memory systems, instruments, memory address/allocation/relocation, etc., can solve problems such as reduced processing speed and complex bus controller structure.

Inactive Publication Date: 2005-12-28
SAMSUNG ELECTRONICS CO LTD
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  • Abstract
  • Description
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Problems solved by technology

[0005] However, the structure of the bus controller becomes complicated and its processing speed decreases because the command scheduler judges whether the order of command processing is determined even in such an infrequent case that when a plurality of masters access the same memory area. Change

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  • Memory control apparatus and method for scheduling commands
  • Memory control apparatus and method for scheduling commands
  • Memory control apparatus and method for scheduling commands

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Embodiment Construction

[0021] The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown, however, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein , these embodiments are provided so that this disclosure will be thorough and complete and fully convey the idea of ​​the present invention to those skilled in the art. The same reference numerals refer to the same parts throughout the drawings.

[0022] figure 1 is a block diagram of a system on chip (SOC) 100 including a plurality of master devices. refer to figure 1 , the SOC 100 includes a plurality of master devices 110 , 112 , and 114 . The master device is a processor that reads commands stored in memory and executes the commands. For example, a central processing unit, video / graphics processor, audio processor, or network processor may be the host device.

[0023] M...

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Abstract

Provided are a memory control apparatus and method for controlling the order in which memory access commands from a plurality of masters are processed to improve processing speed when the memory is accessed by the masters. The memory controller includes: a command queue receiving a memory access command from at least one master device and storing the memory access command; a determination unit analyzing an address of a memory to be accessed by the received command to control an order in which the stored command is processed; and command interpretation A device interprets a command output under the control of the determining unit to output an address-related signal. Therefore, command processing speed is significantly increased without increasing system size.

Description

[0001] This application claims the benefit of Korean Patent Application No. 2004-47623 filed with the Korean Intellectual Property Office on Jun. 24, 2004, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates to command processing, and more particularly, to a memory control apparatus and method for controlling an order in which memory access commands from a plurality of masters are processed when the memory is accessed by the masters to improve command processing speed. Background technique [0003] In a system that includes a processor, the command codes executed by the processor are typically stored in memory, and the processor operates based on the order in which the command codes are interpreted. The processor that executes the commands and accesses the memory is called the master. A single system can include multiple master devices as appropriate. Recently, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02G06F12/00G06F13/16G06F13/18
CPCG06F13/1631G06F12/00G06F12/02
Inventor 姜信旭
Owner SAMSUNG ELECTRONICS CO LTD
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