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Memory controller and data processing system with the same

A technology for a data processing system and a memory controller, applied in the field of memory systems, can solve the problems of consuming a lot of time, slow data transmission, and aggravation.

Inactive Publication Date: 2007-04-25
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This repetitive operation will consume a lot of time
In addition, because the CPU 10 also needs to access pages / blocks of various OneNAND data (through the first memory controller 40), this will further aggravate the impact of slow data transmission on the DRAM 50

Method used

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  • Memory controller and data processing system with the same
  • Memory controller and data processing system with the same
  • Memory controller and data processing system with the same

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Embodiment Construction

[0017] It is to be understood that both the foregoing brief description and the following detailed description are explanatory only, and that the embodiments described herein are not restrictive, but are described by way of example only. Those skilled in the art will appreciate that the presently disclosed methods and systems may be implemented or applied by other embodiments.

[0018] FIG. 3 is a block diagram of a data processing system according to an embodiment of the present disclosure, and FIG. 4 shows a diagram of data transfer from OneNAND flash memory to DRAM in the data processing system shown in FIG. 3 according to an embodiment of the present disclosure. example.

[0019] Referring to FIG. 3 , the data processing system in this embodiment includes a central processing unit (CPU) 110 , direct memory access (DMA) 120 , memory controllers 130 and 140 , DRAM 150 and OneNAND flash memory 160 . DRAM 150 and OneNAND flash memory 160 are controlled by memory controllers 1...

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PUM

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Abstract

In one aspect, a data processing system includes a OneNAND flash memory which includes an internal non-volatile memory and an internal buffer memory which temporarily stores a page data derived from the internal non-volatile memory, and a first memory controller which includes a speed-up buffer. The memory controller controls read operations of the OneNAND flash memory such that the page data stored in the OneNAND internal buffer memory is sequentially and continuously output in multiple data units from the OneNAND flash memory to an exterior device through the speed-up buffer.

Description

technical field [0001] The present disclosure relates generally to memory systems, and more particularly, the present disclosure relates to data processing systems having memory and memory controllers. Background technique [0002] Most of the semiconductor market is focused on the realization of "system-on-a-chip" devices that integrate various functional blocks onto a single chip. An example of a system-on-a-chip is "fused memory". A fused memory is a device that has various memory types (eg, flash memory, ROM, and RAM) but also individual logic blocks, such as timers and / or dedicated communication ports. In addition to the combination of memory and logic circuits, various system specifications can be modified to characterize a related modern fusion memory. Such an adaptive fused memory is also called "OneNAND flash memory", and an example thereof is disclosed on pages 635-652 of the data sheet titled "NAND FLASH MEMORY & SMARTMEDIA" published in September 2003. [0003...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28G06F12/08G06F12/00
Inventor 赵显德金泰均崔永准
Owner SAMSUNG ELECTRONICS CO LTD
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