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Combinatorial logic circuit

A technology of combining logic circuits and circuits, applied in logic circuits, electrical components, electronic switches, etc., can solve the problems of different common-mode voltage levels, large output swings, limitations, etc.

Inactive Publication Date: 2010-05-26
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

We see that due to manufacturing process differences, the common-mode voltage levels at the drains of the output transistors are also different, which can generate additional noise and limit the maximum output swing

Method used

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Examples

Experimental program
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Embodiment Construction

[0025] figure 1 A block diagram of a combinational logic circuit in accordance with the present invention is depicted. The circuit comprises a first logic block B1 coupled to a power supply terminal V through a first resistor R1 and through a second resistor R2 DD , to receive the first and second power supply currents I11, I12 respectively. The circuit also includes a second logic block B2 coupled to the power supply terminal V through a first resistor R1 and through a second resistor R2 DD , to receive the third and fourth power supply currents I22, I21 respectively.

[0026] The first output Q- is coupled to the first block B1 and the first resistor R1. The second output terminal Q+ is coupled to the second logic block B2 and the second resistor R2. A first current source IO is coupled to the first output terminal Q- through a first resistor R1 to provide a first supply current I1 substantially equal to a second supply current I2 through a second resistor R2. It can be...

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PUM

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Abstract

A combinatorial logic circuit includes a first logic block (B1) coupled to a supply terminal (V) by a first resistor device (R1) and a second resistor device (R2) in order to respectively receiving a first and second electrical source currents (I11, I12). The circuit also includes a second logic bloc (B2) coupled to the supply terminal (V) by a first resistor device (R1) and a second resistor device (R2) in order to respectively receiving a third and fourth electrical source currents (I22, I21). A first output terminal (Q-) is coupled to the first block (B1) and the first resistor device (R1). A second output terminal (Q+) is coupled to the second block (B1) and the second resistor (R1). A first current source (I0) is at least coupled to one of the first output terminal (Q-) and / orthe second output terminal (Q+) in order to supply the first electrical source current (I1) through the first resistor device (R1). The first electrical source current (I1) basically equals to the second electrical source current (I2) through the second resistor device (R2).

Description

technical field [0001] The invention relates to a combinational logic circuit. Background technique [0002] Logic circuits are used on a large scale in different applications. The overall development trend of logic circuits is to increase switching speed and reduce power supply voltage to maintain reasonable power consumption in the chip. In addition, in order to obtain the maximum output swing of the signal, the use of differential input and differential output circuits is also increased. [0003] According to the above-mentioned development trend, people have introduced a current-controlled CMOS circuit. US Pat. No. 6,424,194A discloses a family of logic circuits manufactured by conventional CMOS process technology using current-controlled CMOS logic. Various logic circuits are implemented as inverters / buffers, level shifters, NAND (NAND) gates, NOR (NOR) gates, XOR (Exclusive OR) gates, and the like. It can be seen that when the circuit has more than one input differ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/003H03K17/16H03K19/094
CPCH03K19/215H03K19/1738H03K19/082H03K19/0948
Inventor M·A·T·桑杜利努E·斯蒂克武尔特
Owner NXP BV