Image processing module with less line buffers
a processing module and line buffer technology, applied in the field of image processing modules, can solve the problems of redundant, uneconomical, electromagnetic interference, etc., and achieve the effect of less line buffers and avoiding unnecessary cost increas
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
embodiment two
[0035] Referring to FIG. 7, a block diagram of an image processing module according to a second embodiment of the invention is shown. Image processing module 700 includes a timing controller 710 and a scaler 720. The timing controller 710 includes a line buffer 711 and a control unit 712 to control the display panel 230. The present embodiment differs with the first embodiment in that the signal outputted by the scaler 720 differs with that outputted by the scaler 420. The scaler 710 simultaneously outputs the front-scaled image signal Sscf and the back-scaled image signal Sscb of the scaled image signal Ssc to the control unit 712 through a front-channel and a back-channel respectively. Other terms remain unchanged.
embodiment three
[0036] Referring to FIG. 8, a block diagram of an image processing module according to a third embodiment of the invention is shown. Image processing module 800 includes a timing controller 810 and a scaler 820. The timing controller 810 includes a line buffer 811 and a control unit 812 to control the display panel 230. The present embodiment differs with the first embodiment in that the signals received and outputted by the scaler 820 are different from those received and outputted by the scaler 420. The scaler 820 receives the front-storage image signal Sstf and the back-storage image signal Sstb of the storage image signal Sst according to a front-channel and a back-channel respectively, and then outputs the front-scaled image signal Sscf and the back-scaled image signal Sscb of the scaled image signal Ssc to the control unit 812 according to a front-channel and a back-channel respectively.
embodiment four
[0037] Referring to FIG. 9, a block diagram of an image processing module according to a fourth embodiment of the invention is shown. Image processing module 900 is used for receiving an original image signal Si to drive the display panel 930. The image processing module 900 includes a timing controller 910 and a scaler 920. The timing controller 910 receives the original image signal Si, and then outputs a storage image signal Sst′. The scaler 920 receives a storage image signal Sst′ and adjust the resolution of the storage image signal Sst′, then outputs a scaled image signal Ssc′. Then, the timing controller 910 drives a display panel 930 according to the scaled image signal Ssc′. The timing controller 910 includes a line buffer 911 and a control unit 912. The line buffer 911 registers the original image signal Si, and then outputs the storage image signal Sst′. The control unit 912 receives the scaled image signal Ssc′ and outputs a display signal S1, a display signal S2, a disp...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


