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Image processing module with less line buffers

a processing module and line buffer technology, applied in the field of image processing modules, can solve the problems of redundant, uneconomical, electromagnetic interference, etc., and achieve the effect of less line buffers and avoiding unnecessary cost increas

Inactive Publication Date: 2006-07-06
HIMAX TECH LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009] It is therefore the object of the invention to provide an image processing module with less line buffers. Unlike the conventional structure, the image processing structure provided in the invention dispenses with repetition of line buffer thus avoiding unnecessary increase in cost.

Problems solved by technology

However, a few problems, such as electromagnetic interfering, (EMI) for instance, also arise at the same time.
However, in order to meet the standard of high resolution, both the scaler 210 and the timing controller 220 are equipped with a line buffer, which is redundant and uneconomical.

Method used

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Experimental program
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embodiment two

[0035] Referring to FIG. 7, a block diagram of an image processing module according to a second embodiment of the invention is shown. Image processing module 700 includes a timing controller 710 and a scaler 720. The timing controller 710 includes a line buffer 711 and a control unit 712 to control the display panel 230. The present embodiment differs with the first embodiment in that the signal outputted by the scaler 720 differs with that outputted by the scaler 420. The scaler 710 simultaneously outputs the front-scaled image signal Sscf and the back-scaled image signal Sscb of the scaled image signal Ssc to the control unit 712 through a front-channel and a back-channel respectively. Other terms remain unchanged.

embodiment three

[0036] Referring to FIG. 8, a block diagram of an image processing module according to a third embodiment of the invention is shown. Image processing module 800 includes a timing controller 810 and a scaler 820. The timing controller 810 includes a line buffer 811 and a control unit 812 to control the display panel 230. The present embodiment differs with the first embodiment in that the signals received and outputted by the scaler 820 are different from those received and outputted by the scaler 420. The scaler 820 receives the front-storage image signal Sstf and the back-storage image signal Sstb of the storage image signal Sst according to a front-channel and a back-channel respectively, and then outputs the front-scaled image signal Sscf and the back-scaled image signal Sscb of the scaled image signal Ssc to the control unit 812 according to a front-channel and a back-channel respectively.

embodiment four

[0037] Referring to FIG. 9, a block diagram of an image processing module according to a fourth embodiment of the invention is shown. Image processing module 900 is used for receiving an original image signal Si to drive the display panel 930. The image processing module 900 includes a timing controller 910 and a scaler 920. The timing controller 910 receives the original image signal Si, and then outputs a storage image signal Sst′. The scaler 920 receives a storage image signal Sst′ and adjust the resolution of the storage image signal Sst′, then outputs a scaled image signal Ssc′. Then, the timing controller 910 drives a display panel 930 according to the scaled image signal Ssc′. The timing controller 910 includes a line buffer 911 and a control unit 912. The line buffer 911 registers the original image signal Si, and then outputs the storage image signal Sst′. The control unit 912 receives the scaled image signal Ssc′ and outputs a display signal S1, a display signal S2, a disp...

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Abstract

An image processing module with less line buffers is provided. The image processing module receives an original image signal to drive a display panel. The image processing module includes a timing controller and a scaler. The timing controller includes a line buffer and a control unit. The line buffer registers the original image signal and outputs a storage image signal. The scaler receives the storage image signal, adjusts the resolution of the storage image signal, and outputs a scaled image signal to the control unit according to the resolution of the storage image signal. The control unit receives the scaled image signal and outputs a display signal to drive the display panel according to the scaled image signal.

Description

[0001] This application claims the benefit of Taiwan application Serial No. 93138037, filed Dec. 8, 2004, the subject matter of which is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates in general to an image processing module, and more particularly to an image processing module with less line buffers. [0004] 2. Description of the Related Art [0005] If resolution of the image signal is different from the resolution of the display, the resolution must be adjusted in the course of image processing. That is, a scaler is used to adjust the image signal with different resolution to the resolution of the display. Referring to FIG. 1, a block diagram of a conventional image processing system is shown. Image processing system 100 includes a scaler 110 and a timing controller 120. The scaler 110 receives and registers the original image signal Si in the line buffer 111, the original image signal Si is scaled and the r...

Claims

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Application Information

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IPC IPC(8): G09G5/02
CPCG09G3/20G09G2310/08G09G2340/0421
Inventor HUANG, CHUNG-HSUNCHEN, KUEI-HSIANG
Owner HIMAX TECH LTD